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| 7710h?avr?07/2013 features ? high performance, low power avr ? 8-bit microcontroller ? advanced risc architecture ? 129 powerful instructions - most single clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation ? up to 1 mips throughput per mhz ? on-chip 2-cycle multiplier ? data and non-volatile program memory ? 16k bytes flash of in-system programmable program memory ? endurance: 10,000 write/erase cycles ? optional boot code section with independent lock bits ? in-system programming by on-chip boot program ? true read-while-write operation ? 512 bytes of in-system programmable eeprom ? endurance: 100,000 write/erase cycles ? 1024 bytes internal sram ? programming lock for flash pr ogram and eeprom data security ? on chip debug interface (debugwire) ? peripheral features ? two or three 12-bit high speed psc (power stage controllers) with 4-bit resolution enhancement ? non overlapping inverted pwm output pins with flexible dead-time ? variable pwm duty cycle and frequency ? synchronous update of all pwm registers ? auto stop function for event driven pfc implementation ? less than 25hz step width at 150khz output frequency ? psc2 with four output pins and output matrix ? one 8-bit general purpose timer/counter with separate prescaler and capture mode ? one 16-bit general purpose timer/counter with separate prescaler, compare mode and capture mode ? programmable serial usart ? standard uart mode ? 16/17 bit biphase mode for dali communications ? master/slave spi serial interface ? 10-bit adc ? up to 11 single ended channels and 2 fully differential adc channel pairs ? programmable gain (5x, 10x, 20x, 40x on differential channels) ? internal reference voltage ? 10-bit dac ? two or three analog comparator with resistor-array to adjust comparison voltage ? 4 external interrupts ? programmable watchdog timer with separate on-chip oscillator ? special microcontroller features ? low power idle, noise reduction, and power down modes ? power on reset and programmable brown out detection ? flag array in bit-programmable i/o space (4 bytes) ? in-system programmable via spi port ? internal calibrated rc oscillator (8 mhz) ? on-chip pll for fast pwm (32 mhz, 64 mhz) and cpu (16 mhz) ? operating voltage: 2.7v - 5.5v ? extended operating temperature: ? -40c to +105c atmel 8-bit microcontroller with 16k bytes in-system programmable flash at90pwm216 /at90pwm316
2 at90pwm216/316 [datasheet] 7710h?avr?07/2013 1. disclaimer typical values contained in this da tasheet are based on simulations and char acterization of other avr microcon- trollers manufactured on the same process technology. min and max values will be available after the device is characterized. 2. pin configurations figure 2-1. soic 24-pin package product package 12 bit pwm with deadtime adc input adc diff analog comparator application at90pwm216 so24 2 x 2 8 1 2 one fluorescent ballast at90pwm316 so32, qfn32 3 x 2 11 2 3 hid ballast, fluorescent ballast, motor control at90pwm216 soic24 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 (pscout00/xck/ss_a) pd0 (reset/ocd) pe0 (pscin0/clko) pd1 (pscin2/oc1a/miso_a) pd2 (txd/dali/oc0a/ss/mosi_a) pd3 vcc gnd (miso/pscout20) pb0 (mosi/pscout21) pb1 (oc0b/xtal1) pe1 (adc0/xtal2) pe2 (adc1/rxd/dali/icp1a/sck_a) pd4 pb7(adc4/pscout01/sck) pb6 (adc7/icp1b) pb5 (adc6/int2) pb4 (amp0+) pb3 (amp0-) aref agnd avcc pb2 (adc5/int1) pd7 (acmp0) pd6 (adc3/acmpm/int0) pd5 (adc2/acmp2) 3 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 2-2. soic 32-pin package at90pwm316 soic 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 (pscout00/xck/ss_a) pd0 (int3/pscout10) pc0 (reset/ocd) pe0 (pscin0/clko) pd1 (pscin2/oc1a/miso_a) pd2 (txd/dali/oc0a/ss/mosi_a) pd3 (pscin1/oc1b) pc1 vcc gnd (t0/pscout22) pc2 (t1/pscout23) pc3 (miso/pscout20) pb0 (mosi/pscout21) pb1 (oc0b/xtal1) pe1 (adc0/xtal2) pe2 (adc1/rxd/dali/icp1a/sck_a) pd4 pb7(adc4/pscout01/sck) pb6 (adc7/pscout11/icp1b) pb5 (adc6/int2) pc7 (d2a) pb4 (amp0+) pb3 (amp0-) pc6 (adc10/acmp1) aref agnd avcc pc5 (adc9/amp1+) pc4 (adc8/amp1-) pb2 (adc5/int1) pd7 (acmp0) pd6 (adc3/acmpm/int0) pd5 (adc2/acmp2) 4 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 2-3. qfn32 (7*7 mm) package. note: the center gnd paddle has to be connected to gnd. 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 (pscin2/oc1a/miso_a) pd2 (txd/dali/oc0a/ss/mosi_a) pd3 (pscin1/oc1b) pc1 vcc gnd (t0/pscout22) pc2 (t1/pscout23) pc3 (miso/pscout20) pb0 pb4 (amp0+) pb3 (amp0-) pc6 (adc10/acmp1) aref agnd avcc pc5 (adc9/amp1+) pc4 (adc8/amp1-) 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 (mosi/pscout21) pb1 (oc0b/xtal1) pe1 (adc0/xtal2) pe2 (adc1/rxd/dali/icp1_a/sck_a) pd4 (adc2/acmp2 ) pd5 (adc3/acmpm/int0) pd6 (acmp0) pd7 (adc5/int1) pb2 pd1 (pscin0/clko) pe0 (reset/ocd) pc0 (int3/pscout10) pd0 (pscout00/xck/ss_a) pb7 (adc4/pscout01/sck) pb6 (adc7/pscout11/icp1b) pb5 (adc6/int2) pc7 (d2a) 5 at90pwm216/316 [datasheet] 7710h?avr?07/2013 2.1 pin descriptions table 2-1. pin out description s024 pin number so32 pin number qfn32 pin number mnemonic type name, function & alternate function 7 9 5 gnd power ground: 0v reference 18 24 20 agnd power analog ground: 0v reference for analog part 6 8 4 vcc power power supply: 17 23 19 avcc power analog power supply: this is the power supply voltage for analog part for a normal use this pin must be connected. 19 25 21 aref power analog reference: reference for analog converter. this is the reference voltage of the a/d converter. as outpu t, can be used by external analog 8128pboi/o miso (spi master in slave out) pscout20 output 9139pb1i/o mosi (spi master out slave in) pscout21 output 16 20 16 pb2 i/o adc5 (analog input channel5) int1 20 27 23 pb3 i/o amp0- (analog differential amplifier 0 input channel ) 21 28 24 pb4 i/o amp0+ (analog differential amplifier 0 input channel ) 22 30 26 pb5 i/o adc6 (analog input channel 6) int 2 23 31 27 pb6 i/o adc7 (analog input channel 7) icp1b (timer 1 input capture alternate input) pscout11 output (see note 1) 24 32 28 pb7 i/o pscout01 output adc4 (analog input channel 4) sck (spi clock) na 2 30 pc0 i/o pscout10 output (see note 1) int3 7 3 pc1 i/o pscin1 (psc 1 digital input) oc1b (timer 1 output compare b) 10 6 pc2 i/o t0 (timer 0 clock input) pscout22 output 11 7 pc3 i/o t1 (timer 1 clock input) pscout23 output 21 17 pc4 i/o adc8 (analog input channel 8) amp1- (analog differential amplifier 1 input channel) 22 18 pc5 i/o adc9 (analog input channel 9) amp1+ (analog differential amplifier 1 input channel) 26 22 pc6 i/o adc10 (analog input channel 10) acmp1 (analog comparator 1 positive input) 29 25 pc7 i/o d2a : dac output (2) 6 at90pwm216/316 [datasheet] 7710h?avr?07/2013 notes: 1. pscout10 & pscout11 are not present on 24 pins package 2. d2a (dac output) not available on at90pwm261 (soic 24-pins) 3. overview the at90pwm216/316 are low-power cmos 8-bit microcontrollers based on the avr enhanced risc architec- ture. by executing powerful instructions in a sing le clock cycle, the at90pwm216/316 achieves throughputs approaching 1 mips per mhz allowing the system designer to optimize power consum ption versus processing speed. 1 1 29 pd0 i/o pscout00 output (1) xck (uart transfer clock) ss_a (alternate spi slave select) 3 4 32 pd1 i/o pscin0 (psc 0 digital input) clko (system clock output) 451pd2i/o pscin2 (psc 2 digital input) oc1a (timer 1 output compare a) miso_a (programming & alternate spi master in slave out) 562pd3i/o txd (dali/uart tx data) oc0a (timer 0 output compare a) ss (spi slave select) mosi_a (programming & alternat e master out spi slave in) 12 16 12 pd4 i/o adc1 (analog input channel 1) rxd (dali/uart rx data) icp1a (timer 1 input capture) sck_a (programming & alternate spi clock) 13 17 13 pd5 i/o adc2 (analog input channel 2) acmp2 (analog comparator 2 positive input) 14 18 14 pd6 i/o adc3 (analog input channel 3 ) acmpm reference for analog comparators int0 15 19 15 pd7 i/o acmp0 (analog comparator 0 positive input) 2 3 31 pe0 i/o or i reset (reset input) ocd (on chip debug i/o) 10 14 10 pe1 i/o xtal1: xtal input oc0b (timer 0 output compare b) 11 15 11 pe2 i/o xtal2: xtal output adc0 (analog input channel 0) table 2-1. pin out description (continued) s024 pin number so32 pin number qfn32 pin number mnemonic type name, function & alternate function 7 at90pwm216/316 [datasheet] 7710h?avr?07/2013 3.1 block diagram figure 3-1. block diagram the avr core combines a rich instruction set with 32 general purpose working registers. all the 32 registers are directly connected to the ar ithmetic logic unit (alu), allowing two independent regi sters to be accessed in one single instruction executed in one clock cycle. the result ing architecture is more c ode efficient wh ile achieving throughputs up to ten times faster th an conventional cisc microcontrollers. the at90pwm216/316 provides the following features: 16k bytes of in-system programmable flash with read- while-write capabilities, 512 bytes e eprom, 1024 bytes sram, 53 general purpose i/o lines, 32 general purpose working registers, three power stage controllers, two flexible timer/counters with compare modes and pwm, one usart with dali mode, an 11-channel 10-bit adc with tw o differential input stage with programmable gain, a 10- bit dac, a programmable watc hdog timer with internal oscillator, an spi serial po rt, an on-chip debug system and four software selectable power saving modes. the idle mode stops the cpu while allowing the sram, ti mer/counters, spi ports and interrupt system to con- tinue functioning. the power-down mode saves the register contents but freezes the osc illator, disabling all other chip functions until the next interrupt or hardware reset. the adc noise reduction mode stops the cpu and all i/o modules except adc, to minimize switching noise during adc conversions. in standby mode, the crystal/res- 16kx8 flash program memory instruction register instruction decoder program counter control lines 32 x 8 general purpose registrers alu status and control i/o lines eeprom 512 bytes data bus 8-bit data sra m 1024 bytes direct addressing indirect addressing interrupt unit spi unit watchdog timer 3 analog comparators dac adc psc 2/1/0 timer 1 timer 0 dali usart 8 at90pwm216/316 [datasheet] 7710h?avr?07/2013 onator oscillator is running while the rest of the device is sleeping. this allows very fast star t-up combin ed with low power consumption. the device is manufactured using the atmel high-density nonvolatile me mory technology. the on-chip isp flash allows the program memory to be reprogrammed in-system through an spi serial interface, by a conventional non- volatile memory programmer, or by an on-chip boot program running on the avr core. the boot program can use any interface to download the application program in the application flash memory. software in the boot flash section will continue to run while the application flash section is updated, providing true read-while-write opera- tion. by combining an 8-bit risc cpu with in-system self-programmable flash on a monolithic chip, the atmel at90pwm216/316 is a powerful microcontroller that provides a highly fl exible and cost effective solution to many embedded control applications. the at90pwm216/316 avr is supported with a full suite of program and system devel opment tools including: c compilers, macro assemblers, program debugger/simulato rs, in-circuit emulators, and evaluation kits. note: at90pwm216 device is available in soic 24-pin package an d does not have the d2a (dac output) brought out to i/0 pins. 3.2 pin descriptions 3.2.1 vcc digital supply voltage. 3.2.2 gnd ground. 3.2.3 port b (pb7..pb0) port b is an 8-bit bi-directional i/o port with internal pull- up resistors (selected for each bit). the port b output buf- fers have symmetrical drive ch aracteristics with both high si nk and source capability. as i nputs, port b pins that are externally pulled low will source current if the pull-up resistor s are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b also serves the functions of various spec ial features of the at90pwm216/316 as listed on page 63 . 3.2.4 port c (pc7..pc0) port c is an 8-bit bi-directional i/o port with internal pull- up resistors (selected for each bit). the port c output buf- fers have symmetrical drive characteristi cs with both high sink and source capability. as input s, port c pins that are externally pulled low will source current if the pull-up resistors are activate d. the port c pins are tri-stated when a reset condition becomes active, even if the clock is not running. port c is not available on 24 pins package. port c also serves the functions of specia l features of the at90pwm316 as listed on page 65 . 3.2.5 port d (pd7..pd0) port d is an 8-bit bi-directional i/o port with internal pull- up resistors (selected for each bit). the port d output buf- fers have symmetrical drive characteristi cs with both high sink and source capability. as input s, port d pins that are externally pulled low will source current if the pull-up resistors are activate d. the port d pins are tri-stated when a reset condition becomes active, even if the clock is not running. port d also serves the functions of various spec ial features of the at90 pwm216/316 as listed on page 68 . 9 at90pwm216/316 [datasheet] 7710h?avr?07/2013 3.2.6 port e (pe2..0) reset/ xtal1/ xtal2 port e is an 3-bit bi-directional i/o port with internal pull- up resistors (selected for each bit). the port e output buf- fers have symmetrical drive ch aracteristics with both high si nk and source capability. as i nputs, port e pins that are externally pulled low will source current if the pull-up resistor s are activated. the port e pins are tri-stated when a reset condition becomes active, even if the clock is not running. if the rstdisbl fuse is programmed, pe0 is used as an i/o pin. note that the electrical characteristics of pe0 dif- fer from those of the other pins of port c. if the rstdisbl fuse is unprogrammed, pe0 is used as a reset input. a low level on th is pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. the minimum pulse length is given in table 8-1 on page 41 . shorter pulses are not guaranteed to generate a reset. depending on the cl ock selection fuse settings, pe1 can be used as input to the in verting oscillator amplifier and input to the internal clock operating circuit. depending on the clock selection fuse settings, pe2 can be used as output fr om the inverting o scillator amplifier. the various special features of port e are elaborated in ?alternate functions of port e? on page 71 and ?clock sys- tems and their distribution? on page 25 . 3.2.7 avcc avcc is the supply voltage pin for the a/d conver ter. it should be externally connected to v cc , even if the adc is not used. if the adc is used, it should be connected to v cc through a low-pass filter. 3.2.8 aref this is the analog reference pin for the a/d converter. 3.3 about code examples this documentation contains simple co de examples that briefly show how to use various parts of the device. these code examples assume that the part specific header file is included before compilation. be aware that not all c compiler vendors include bit definitions in the header files and interrupt handling in c is compiler dependent. please confirm with the c compile r documentation for more details. 10 at90pwm216/316 [datasheet] 7710h?avr?07/2013 4. avr cpu core 4.1 introduction this section discusses the avr core ar chitecture in general. the main function of the cpu core is to ensure cor- rect program execution. the cpu mu st therefore be able to access memo ries, perform calculations, control peripherals, and handle interrupts. 4.2 architectural overview figure 4-1. block diagram of the avr architecture in order to maximize performance and parallelism, the avr uses a harvard architecture ? with separate memories and buses for program and data. instructions in the program memory are executed with a single level pipelining. while one instruction is being executed , the next instruction is pre-fetched from the program memory. this concept enables instructions to be executed in every clock cycl e. the program memory is in-system reprogrammable flash memory. the fast-access register file contai ns 32 x 8-bit general purpose work ing registers with a single clock cycle access time. this allows singl e-cycle arithmetic logic unit (alu) operation. in a typi cal alu operation, two oper- flash program memory instruction register instruction decoder program counter control lines 32 x 8 general purpose registrers alu status and control i/o lines eeprom data bus 8-bit data sram direct addressing indirect addressing interrupt unit spi unit watchdog timer analog comparator i/o module 2 i/o module1 i/o module n 11 at90pwm216/316 [datasheet] 7710h?avr?07/2013 ands are output from the register file, the operation is ex ecuted, and the result is stored back in the register file ? in one clock cycle. six of the 32 registers can be used as three 16-bit indirect address register pointers for data space addressing ? enabling efficient address calculations. one of the these address pointers can also be used as an address pointer for look up tables in flash program memory. these added f unction registers are the 16-bit x-, y-, and z-register, described later in this section. the alu supports arithmetic and logi c operations between registers or bet ween a constant and a register. single register operations can also be executed in the alu. afte r an arithmetic operation, t he status regist er is updated to reflect information about the result of the operation. program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. most avr inst ructions have a single 16-bit word format. every program memory address contains a 16- or 32-bit instruction. program flash memory space is divided in two sections, the boot program section and the application program section. both sections have dedicated lock bits for writ e and read/write protection. the spm (store program mem- ory) instruction that writes into th e application flash memory section must reside in the boot program section. during interrupts and subroutine calls, the return address program counter (pc) is stored on the stack. the stack is effectively allocated in the general data sram, and c onsequently the stack size is only limited by the total sram size and the usage of the sram. all user programs must initialize the sp in the reset routine (before sub- routines or interrupts are executed). the stack pointer (sp) is read/write accessible in the i/o space. the data sram can easily be accessed through the five different addressing modes supported in the avr architecture. the memory spaces in the avr architecture are all linear and regular memory maps. a flexible interrupt module has its contro l registers in the i/o space with an additional global interrupt enable bit in the status register. all interrupts have a separate in terrupt vector in the interrupt vector table. the interrupts have priority in accordance with their interrupt vector position . the lower the interrupt vector address, the higher is the priority. the i/o memory space contains 64 addresses for cpu peripheral functions as control registers, spi, and other i/o functions. the i/o memory can be accessed directly, or as the data space locations following those of the reg- ister file, 0x20 - 0x5f. in addition, the at90pwm216/ 316 has extended i/o space from 0x60 - 0xff in sram where only the st/sts/std and ld/lds/ldd instructions can be used. 4.3 alu ? arithm etic logic unit the high-performance avr alu operates in direct connection with all the 32 general purpose working registers. within a single clock cycle, arithmetic operations between general purpose re gisters or between a register and an immediate are executed. the alu operat ions are divided into three main cat egories ? arithmetic, logical, and bit- functions. some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. see the ?instruction set? section for a detailed description. 4.4 status register the status register contains information about the result of the most re cently executed arithmetic instruction. this information can be used for altering program flow in order to perform conditional operations. note that the status register is updated afte r all alu operations, as specif ied in the instruction set refe rence. this will in many cases remove the need for using the dedicated compare instruct ions, resulting in faster and more compact code. the status register is not automatically stored when entering an inte rrupt routine and restored when returning from an interrupt. this must be handled by software. 12 at90pwm216/316 [datasheet] 7710h?avr?07/2013 the avr status register ? sreg ? is defined as: ? bit 7 ? i: global interrupt enable the global interrupt enable bit must be set to enabled the interrupts. the individual interrupt enable control is then performed in separate control registers. if the global interr upt enable register is cleared, none of the interrupts are enabled independent of the individual inte rrupt enable settings. the i-bit is cleared by hardware after an interrupt has occurred, and is set by the reti instruction to enab le subsequent interrupts. the i-bit can also be set and cleared by the application with the sei and cli instructions, as described in the instruction set reference. ? bit 6 ? t: bit copy storage the bit copy instructions bld (bit load) and bst (bit st ore) use the t-bit as source or destination for the oper- ated bit. a bit from a register in the register file can be copied into t by the bst inst ruction, and a bit in t can be copied into a bit in a register in the register file by the bld instruction. ? bit 5 ? h: half carry flag the half carry flag h indicates a half carry in some arithmetic operations. ha lf carry is useful in bcd arithmetic. see the ?instruction set descrip tion? for detaile d information. ? bit 4 ? s: sign bit, s = n ?? v the s-bit is always an exclusive or between the negative flag n and the tw o?s complement overflow flag v. see the ?instruction set description? for detailed information. ? bit 3 ? v: two?s complement overflow flag the two?s complement overflow flag v supports two?s co mplement arithmetics. see t he ?instruction set descrip- tion? for detailed information. ? bit 2 ? n: negative flag the negative flag n indicates a negative result in an ar ithmetic or logic operation. see the ?instruction set description? for det ailed information. ? bit 1 ? z: zero flag the zero flag z indicates a zero result in an arithmetic or logic operation. see the ?ins truction set description? for detailed information. ? bit 0 ? c: carry flag the carry flag c indicates a carry in an arithmetic or l ogic operation. see the ?instruction set description? for detailed information. 4.5 general purpose register file the register file is optimized for the avr enhanced risc instruction set. in order to achieve the required perfor- mance and flexibility, the followin g input/output scheme s are supported by the register file: ? one 8-bit output operand and one 8-bit result input ? two 8-bit output operands and one 8-bit result input ? two 8-bit output operands and one 16-bit result input ? one 16-bit output operand and one 16-bit result input bit 76543210 i t h s v n z c sreg read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 13 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 4-2 shows the structure of the 32 genera l purpose working registers in the cpu. figure 4-2. avr cpu general purpose working registers most of the instructions oper ating on the register file have direct access to all registers, and most of them are sin- gle cycle instructions. as shown in figure 4-2 , each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user data space. although not bei ng physically implemented as sram locations, this memory organization provides great flexibility in access of the registers, as the x-, y- and z-pointer registers can be set to index any register in the file. 4.5.1 the x-register, y-register, and z-register the registers r26..r31 have some added functions to their general purpos e usage. these registers are 16-bit address pointers for indirect addressing of the data space. the three indirect address registers x, y, and z are defined as described in figure 4-3 . figure 4-3. the x-, y-, and z-registers in the different addressing modes thes e address registers have functions as fixed displacement, automatic incre- ment, and automatic decrement (see the instruction set reference for details). 70addr. r0 0x00 r1 0x01 r2 0x02 ? r13 0x0d general r14 0x0e purpose r15 0x0f working r16 0x10 registers r17 0x11 ? r26 0x1a x-register low byte r27 0x1b x-register high byte r28 0x1c y-register low byte r29 0x1d y-register high byte r30 0x1e z-register low byte r31 0x1f z-register high byte 15 xh xl 0 x-register 7 0 7 0 r27 (0x1b) r26 (0x1a) 15 yh yl 0 y-register 7 0 7 0 r29 (0x1d) r28 (0x1c) 15 zh zl 0 z-register 7 0 7 0 r31 (0x1f) r30 (0x1e) 14 at90pwm216/316 [datasheet] 7710h?avr?07/2013 4.6 stack pointer the stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. the stack pointer register alwa ys points to the top of th e stack. note that the stack is implemented as growing from higher memory loca tions to lower memory loca tions. this implies that a stack push command decr eases the stack pointer. the stack pointer points to the data sram stack area where the subroutine and interrupt stacks are located. this stack space in the data sram must be defined by the pr ogram before any subroutine calls are executed or inter- rupts are enabled. the stack pointer must be set to poi nt above 0x100. the stack pointer is decremented by one when data is pushed onto the stack with the push instru ction, and it is decremented by two when the return address is pushed onto the stack with s ubroutine call or interrupt. the stack pointer is incremented by one when data is popped from the stack with the pop instruction, an d it is incremented by two when data is popped from the stack with return from subroutine re t or return from interrupt reti. the avr stack pointer is implemented as two 8-bit registers in the i/o space. the number of bits actually used is implementation dependent. note that the data space in so me implementations of the avr architecture is so small that only spl is needed. in this case , the sph register will not be present. 4.7 instruction execution timing this section describes the general acce ss timing concepts for instruction exec ution. the avr cpu is driven by the cpu clock clk cpu , directly generated from the selected clock source for the chip. no internal clock division is used. figure 4-4 shows the parallel instruction fetches and instruct ion executions enabled by the harvard architecture and the fast-access register file concept. this is the basic pipelining concept to obtain up to 1 mips per mhz with the correspondin g unique results for functions per cost, functions per clocks, and functions per power-unit. figure 4-4. the parallel instruction fetches and instruction executions figure 4-5 shows the internal timing concept for the register file. in a single clock cycle an alu operation using two register operands is executed, and the result is stored back to the destination register. bit 1514131211109 8 sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sph sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 spl 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 00000000 clk 1st instruction fetch 1st instruction execute 2nd instruction fetch 2nd instruction execute 3rd instruction fetch 3rd instruction execute 4th instruction fetch t1 t2 t3 t4 cpu 15 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 4-5. single cycle alu operation 4.8 reset and in terrupt handling the avr provides several different interrupt sources. thes e interrupts and the separate reset vector each have a separate program vector in the program memory space. all interrupts are assigned individual enable bits which must be written logic one together with the global interrupt enable bit in the status register in order to enable the interrupt. depending on the program counter value, interr upts may be automatically disa bled when boot lock bits blb02 or blb12 are programmed. this feature improves software security. see the section ?memory program- ming? on page 265 for details. the lowest addresses in the program memory space are by default defined as the reset and interrupt vectors. the complete list of vectors is shown in ?interrupts? on page 51 . the list also determines the priority levels of the different interrupts. the lower the address the hi gher is the priority level. reset has the highest priority, and next is psc2 capt ? the psc2 capture event. the interrupt vect ors can be moved to the start of the boot flash sec- tion by setting the ivsel bit in the mcu control register (mcucr). refer to ?interrupts? on page 51 for more information. the reset vector can also be moved to the start of the boot flash section by programming the bootrst fuse, see ?boot loader support ? read-while-write self-programming? on page 251 . 4.8.1 interrupt behavior when an interrupt occurs, the global interrupt enable i-bit is cleared and all interrupts are disabled. the user soft- ware can write logic one to the i-bit to enable nested inte rrupts. all enabled interrupts can then interrupt the current interrupt routine. the i-bit is automatically set when a return from interrupt instruction ? reti ? is executed. there are basically two types of interrupts. the first type is triggered by an event that sets the interrupt flag. for these interrupts, the program counter is vectored to the ac tual interrupt vector in order to execute the interrupt handling routine, and hardware clears the corresponding inte rrupt flag. interrupt flags can also be cleared by writ- ing a logic one to the flag bit position(s) to be cleared. if an interrupt condition occurs while the corresponding interrupt enable bit is cleare d, the interrupt flag will be se t and remembered until the interrupt is enabled, or the flag is cleared by software. similarly, if one or more interrup t conditions occur while the gl obal interrupt enable bit is cleared, the corresponding in terrupt flag(s) will be set and remembered until the global in terrupt enable bit is set, and will then be executed by order of priority. the second type of interrupts will trigger as long as the interrupt condition is present. these inte rrupts do not nec- essarily have interrupt flags. if the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. when the avr exits from an inte rrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. note that the status regist er is not automatically stored when enteri ng an interrupt routine, nor restored when returning from an interrupt routine. this must be handled by software. total execution time register operands fetch alu operation execute result write back t1 t2 t3 t4 clk cpu 16 at90pwm216/316 [datasheet] 7710h?avr?07/2013 when using the cli instruction to disabl e interrupts, the in terrupts will be immediately disabled. no interrupt will be executed after the cli instru ction, even if it occurs simultaneously wit h the cli instruction. the following example shows how this can be used to avoid interr upts during the timed eeprom write sequence.. when using the sei instruction to enabl e interrupts, the instruct ion following sei will be ex ecuted before any pend- ing interrupts, as shown in this example. 4.8.2 interrupt response time the interrupt execution response for all the enabled avr inte rrupts is four clock cycles minimum. after four clock cycles the program vector address for the actual interrupt handling routine is executed. during this four clock cycle period, the program counter is pushed onto the stack. the vector is norma lly a jump to the interrupt routine, and this jump takes three clock cycles. if an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. if an interrup t occurs when the mcu is in sleep mode, the interrupt exe- cution response time is increased by four clock cycles. this increase comes in addition to the start-up time from the selected sleep mode. a return from an interrupt handling routine takes four clock cycles. during these four clock cycles, the program counter (two bytes) is popped back from the stack, the st ack pointer is incremented by two, and the i-bit in sreg is set. assembly code example in r16, sreg ; store sreg value cli ; disable interrupts during timed sequence sbi eecr, eemwe ; start eeprom write sbi eecr, eewe out sreg, r16 ; restore sreg value (i-bit) c code example char csreg; csreg = sreg; /* store sreg value */ /* disable interrupts during timed sequence */ _cli(); eecr |= (1< 18 at90pwm216/316 [datasheet] 7710h?avr?07/2013 the lower 768 data memory locations address both the register file, the i/o memo ry, extended i/o memory, and the internal data sram. the first 32 locations address the register file, the next 64 location the standard i/o memory, then 160 locations of extended i/o memory, and the next 512 locations address the internal data sram. the five different addressing modes for the data memory cover: direct, indirect with displacement, indirect, indi- rect with pre-decrement, and indirect wi th post-increment. in the register fi le, registers r26 to r31 feature the indirect addressing pointer registers. the direct addressing reaches the entire data space. the indirect with displacement mode reaches 63 address lo cations from the base address given by the y- or z- register. when using register indirect addressing modes with au tomatic pre-decrement and post-increment, the address registers x, y, and z are decremented or incremented. the 32 general purpose working registers, 64 i/o regist ers, 160 extended i/o regi sters, and the 512 bytes of internal data sram in the at90pwm216/316 are all ac cessible through all these addressing modes. the register file is described in ?general purpose register file? on page 12 . figure 5-2. data memory map 5.2.1 sram data access times this section describes the general acce ss timing concepts for internal memo ry access. the internal data sram access is performed in two clk cpu cycles as described in figure 5-3 . figure 5-3. on-chip data sram access cycles 32 registers 64 i/o registers internal sram (1024 x 8) 0x0000 - 0x001f 0x0020 - 0x005f 0x04ff 0x0060 - 0x00ff data memory 160 ext i/o reg. 0x0100 clk wr rd data data address address valid t1 t2 t3 compute address read write cpu memory access instruction next instruction 19 at90pwm216/316 [datasheet] 7710h?avr?07/2013 5.3 eeprom data memory the at90pwm216/316 contains 512 bytes of data eeprom memory. it is organized as a separate data space, in which single bytes can be read and written. the eeprom has an endurance of at least 100,000 write/erase cycles. the access between the eepr om and the cpu is described in the following, specifying the eeprom address registers, the eeprom data register, and the eeprom control register. for a detailed description of spi and para llel data downloading to the eeprom, see ?serial downloading? on page 279 , and ?parallel programming parameters, pin mapping, and commands? on page 268 respectively. 5.3.1 eeprom read/write access the eeprom access registers are accessible in the i/o space. the write access time for the eeprom is given in table 5-2 . a self-timing function, however, lets the user software detect when the next byte can be writ ten. if the user code c ontains instructions that write the eeprom, some pre- cautions must be taken. in he avily filtered power supplies, v cc is likely to rise or fall slowly on power-up/down. this causes the device for some period of time to run at a voltage lower than specified as minimum for the clock fre- quency used. for details on how to avoi d problems in these situations see see ?preventing eeprom corruption? on page 23. in order to prevent unintentional eeprom writes, a specific write procedure must be followed. refer to the description of the eepr om control register for details on this. when the eeprom is read, the cpu is ha lted for four clock cycles before t he next instruction is executed. when the eeprom is written, the cpu is halted for two clock cycles before the next instruction is executed. 5.3.2 the eeprom address registers ? eearh and eearl ? bits 15..9 ? reserved bits these bits are reserved bits in the at90pwm2 16/316 and will always read as zero. ? bits 8..0 ? eear8..0: eeprom address the eeprom address registers ? ee arh and eearl specify the eeprom address in the 512 bytes eeprom space. the eeprom data bytes are ad dressed linearly between 0 and 511. th e initial value of eear is undefined. a proper value must be written be fore the eeprom ma y be accessed. 5.3.3 the eeprom data register ? eedr ? bits 7..0 ? eedr7.0: eeprom data for the eeprom write operation, the eedr register contains the data to be written to the eeprom in the address given by the eear register. for the eeprom read operation, the ee dr contains the data read out from the eeprom at the ad dress given by eear. bit 15141312 11 10 9 8 ? ? ? ? ? ? ? eear8 eearh eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 eearl 7654 3 2 10 read/write r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 x xxxx x x xx bit 76543210 eedr7 eedr6 eedr5 eedr4 eedr3 eedr2 eedr1 eedr0 eedr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 20 at90pwm216/316 [datasheet] 7710h?avr?07/2013 5.3.4 the eeprom control register ? eecr ? bits 7..6 ? reserved bits these bits are reserved bits in the at90pwm2 16/316 and will always read as zero. ? bits 5..4 ? eepm1 and eepm0: eeprom programming mode bits the eeprom programming mode bit setting defines whic h programming action that will be triggered when writing eewe. it is possible to program data in one atomic op eration (erase the old value and program the new value) or to split the erase and write operations in two different operations. the programming times for the different modes are shown in table 5-1 . while eewe is set, any write to eepmn will be ignored. during re set, the eepmn bits will be reset to 0b00 unless th e eeprom is busy programming. ? bit 3 ? eerie: eeprom ready interrupt enable writing eerie to one enables the eeprom ready interrupt if the i bit in sreg is set. writing eerie to zero dis- ables the interrupt. the eeprom ready interrupt ge nerates a constant interrupt when eewe is cleared. the interrupt will not be generat ed during eeprom write or spm. ? bit 2 ? eemwe: eeprom master write enable the eemwe bit determines wh ether setting eewe to one causes the eeprom to be written. when eemwe is set, setting eewe within four clock cycles will write data to the eeprom at the sele cted address if eemwe is zero, setting eewe will have no effect. when eemwe has been written to one by software, hardware clears the bit to zero after four clock cycles. see the descript ion of the eewe bit for an eeprom write procedure. ? bit 1 ? eewe: eeprom write enable the eeprom write enable signal eewe is the write st robe to the eeprom. when address and data are cor- rectly set up, the eewe bit must be written to one to write the value into the eeprom. the eemwe bit must be written to one before a logical one is written to eewe, otherw ise no eeprom write takes place. the following pro- cedure should be followed when writing the eeprom (the order of steps 3 and 4 is not essential): 1. wait until eewe becomes zero. 2. wait until spmen (store program memory enable) in spmcsr (store program memory control and sta- tus register) becomes zero. 3. write new eeprom addres s to eear (optional). 4. write new eeprom data to eedr (optional). 5. write a logical one to the eemwe bit while writing a zero to eewe in eecr. 6. within four clock cycles after sett ing eemwe, write a logical one to eewe. bit 76543210 ? ? eepm1 eepm0 eerie eemwe eewe eere eecr read/write r r r/w r/w r/w r/w r/w r/w initial value 0 0 x x 0 0 x 0 table 5-1. eeprom mode bits eepm1 eepm0 programming time operation 0 0 3.4 ms erase and write in one operation (atomic operation) 0 1 1.8 ms erase only 1 0 1.8 ms write only 1 1 ? reserved for future use 21 at90pwm216/316 [datasheet] 7710h?avr?07/2013 the eeprom can not be programmed during a cpu write to the flash memory. the software must check that the flash programming is completed before initiating a ne w eeprom write. step 2 is only relevant if th e software con- tains a boot loader allowing the cpu to program the flash. if the flash is never being updated by the cpu, step 2 can be omitted. see ?boot loader support ? read-while-write self-programming? on page 251 for details about boot programming. caution: an interrupt between step 5 and st ep 6 will make the write cycle fa il, since the eeprom master write enable will time-out. if an interrupt r outine accessing the eeprom is inte rrupting another eeprom access, the eear or eedr register will be modifi ed, causing the interrupted eeprom a ccess to fail. it is recomme nded to have the global interrupt flag cleared during all the steps to avoid these problems. when the write access time has elapsed, the eewe bit is cleared by hardware. the user software can poll this bit and wait for a zero before writing the next byte. when eewe has been se t, the cpu is halted for two cycles before the next instruction is executed. ? bit 0 ? eere: eeprom read enable the eeprom read enable signal eere is the read strobe to the eeprom. when the co rrect address is set up in the eear register, the eere bit must be written to a logic one to trig ger the eeprom read. the eeprom read access takes one instruction, and the requested data is available immediately. when the eeprom is read, the cpu is halted for four cycles before the next instruction is executed. the user should poll the eewe bit before starting the read oper ation. if a write operation is in progress, it is neither possible to read t he eeprom, nor to change the eear register. the calibrated oscillator is used to time the eeprom accesses. table 5-2 lists the typical programming time for eeprom access from the cpu. the following code examples show one assembly and one c function for writing to the eeprom. the examples assume that interrupts are controlled (e .g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. the examples also assume that no flash boot loader is present in the software. if such code is present, th e eeprom write function must also wait for any ongoing spm command to finish. table 5-2. eeprom programming time. symbol number of calibrated rc oscillator cycles typ programming time eeprom write (from cpu) 26368 3.3 ms 22 at90pwm216/316 [datasheet] 7710h?avr?07/2013 table 3. assembly code example eeprom_write: ; wait for completion of previous write sbic eecr,eewe rjmp eeprom_write ; set up address (r18:r17) in address register out eearh, r18 out eearl, r17 ; write data (r16) to data register out eedr,r16 ; write logical one to eemwe sbi eecr,eemwe ; start eeprom write by setting eewe sbi eecr,eewe ret c code example void eeprom_write ( unsigned int uiaddress, unsigned char ucdata) { /* wait for completion of previous write */ while(eecr & (1< 25 at90pwm216/316 [datasheet] 7710h?avr?07/2013 6. system clock 6.1 clock systems and their distribution figure 6-1 presents the principal clock systems in the avr and their distribution. all of the clocks need not be active at a given time. in order to r educe power consumption, the clocks to u nused modules can be halted by using different sleep modes, as described in ?power management and sleep modes? on page 35 . the clock systems are detailed below. figure 6-1. clock distribution at90pwm216/316 6.1.1 cpu clock ? clk cpu the cpu clock is routed to parts of the system concerned with operation of the avr core. examples of such mod- ules are the general purpose register file, the status register and the data memory holding the stack pointer. halting the cpu clock inhibits the core from performing general operations and calculations. 6.1.2 i/o clock ? clk i/o the i/o clock is used by the majority of the i/o modules, like timer/counters, spi, usart. the i/o clock is also used by the external interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detecte d even if the i/o clock is halted. 6.1.3 flash clock ? clk flash the flash clock controls operation of th e flash interface. the flas h clock is usually active simultaneously with the cpu clock. general i/o modules adc cpu core ram clk i/o a v r clock control unit clk cpu flash and eeprom clk flash clk adc source clock watchdog timer watchdog oscillator reset logic clock multiplexer watchdog clock calibrated rc oscillator (crystal oscillator) external clock psc0/1/2 pll clk pll multiplexer pll input 26 at90pwm216/316 [datasheet] 7710h?avr?07/2013 6.1.4 pll clock ? clk pll the pll clock allows the psc modules to be clocked dire ctly from a 64/32 mhz cloc k. a 16 mhz clock is also derived for the cpu. 6.1.5 adc clock ? clk adc the adc is provided with a dedicated clock domain. this a llows halting the cpu and i/o clocks in order to reduce noise generated by digital circuitry. this gives more accurate adc conversion results. 6.2 clock sources the device has the following clock source options, selectable by fl ash fuse bits as illustrated by table 6-1 the clock from the selected source is input to the avr clock generator, and routed to the appropriate modules. the various choices for each clocking option is given in the followin g sections. when the cpu wakes up from power-down or power-save, the selected clock source is used to time the st art-up, ensuring st able oscillator oper- ation before instruction execution starts . when the cpu starts from reset, there is an additional delay allowing the power to reach a stable level before starting normal operation. the watchdog oscillato r is used for timing this real- time part of the start-up time. t he number of wdt oscillator cycles used for each time-out is shown in table 6-2 . the frequency of the watchdog oscillator is voltage dependent as shown in ?watchdog oscillator frequency vs. vcc? on page 312 . table 6-1. device clocking option s select at90pwm216/316 device clocking option system clock pll input cksel3..0 (1) 1.for all fuses ?1? means unprogrammed while ?0? means programmed external crystal/ceramic resonator ext osc (2) 2.ext osc : external osc rc osc (3) 3.rc osc : internal rc oscillator 1111 - 1000 pll output divided by 4 : 16 mhz / pll driven by external crystal/ceramic resonator ext osc ext osc 0100 pll output divided by 4 : 16 mhz / pll driven by external crystal/ceramic resonator pll / 4 ext osc 0101 reserved n/a n/a 0111- 0110 pll output divided by 4 : 16 mhz pll / 4 rc osc 0011 calibrated internal rc oscillator rc osc rc osc 0010 pll output divided by 4 : 16 mhz / pll driven by external clock pll / 4 ext clk (4) 4.ext clk : external clock input 0001 external clock ext clk rc osc 0000 table 6-2. number of watchdog oscillator cycles typ time-out (v cc = 5.0v) typ time-out (v cc = 3.0v) number of cycles 65 ms 69 ms 8k (8,192) 27 at90pwm216/316 [datasheet] 7710h?avr?07/2013 6.3 default clock source the device is shipped with cksel = ?0 010?, sut = ?10?, and ck div8 programmed. the default cl ock source set- ting is the internal rc oscillator with lo ngest start-up time and an initial system clock prescaling of 8. this default setting ensures that all users can make their desired clock source setting using an in-system or parallel programmer. 6.4 low power cr ystal oscillator xtal1 and xtal2 are input and output, respectively, of an inverting amplifier which c an be configured for use as an on-chip oscillator, as shown in figure 6-2 . either a quartz crystal or a ceramic resonator may be used. this crystal oscillator is a low power oscillator, with reduced voltage swing on the xtal2 output. it gives the low- est power consumption, but is not ca pable of driving other clock inputs. c1 and c2 should always be equal fo r both crystals and resonators. the optimal value of the capacitors depends on the crystal or resonator in use, the amount of stra y capacitance, and the electrom agnetic noise of the environ- ment. some initial guidelines for choosing capacitors for use with crystals are given in table 6-3 . for ceramic resonators, the capacitor values given by the manufact urer should be used. for more information on how to choose capacitors and other details on oscillator operation, refe r to the multi-purpose os cillator application note. figure 6-2. crystal oscillator connections the oscillator can operate in three diff erent modes, each optimized for a s pecific frequenc y range. t he operating mode is selected by the fu ses cksel3..1 as shown in table 6-3 . notes: 1. the frequency ranges are preliminary values. 2. this option should not be used with cr ystals, only with ceramic resonators. the cksel0 fuse together with the sut1..0 fuses select th e start-up times as shown in table 6-4 . table 6-3. crystal oscillator operating modes cksel3..1 frequency range (1) (mhz) recommended range for capacitors c1 and c2 for use with crystals (pf) 100 (2) 0.4 - 0.9 ? 101 0.9 - 3.0 12 - 22 110 3.0 - 8.0 12 - 22 111 8.0 -16.0 12 - 22 xtal2 xtal1 gnd c2 c1 28 at90pwm216/316 [datasheet] 7710h?avr?07/2013 notes: 1. these options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the applicat ion. these options are not suitable for crystals. 2. these options are intended for use wit h ceramic resonators and will ensure frequency stability at start-up. they can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency sta- bility at start-up is not important for the application. 6.5 calibrated internal rc oscillator by default, the internal rc oscillator provides an approximate 8.0 mhz clock. though voltage and temperature dependent, this clock can be very accurately calibrated by the user. the device is shipped with the ckdiv8 fuse programmed. see ?system clock prescaler? on page 32 for more details. this clock may be selected as the system cloc k by programming the cksel fuses as shown in table 6-5 . if selected, it will operate with no extern al components. during reset, hardwa re loads the pre-pr ogrammed calibration value into the osccal register and ther eby automatically calibrates the rc os cillator. the accuracy of this cali- bration is shown as factory calibration in table 25-1 on page 285 . by changing the osccal register from sw, see ?oscillator calibration regi ster ? osccal? on page 29 , it is pos- sible to get a higher calibration accuracy than by using th e factory calibration. the accu racy of this calibration is shown as user calibration in section ?calibration byte?, page 268 . when this oscillator is used as the chip clock, the watchdog oscillator will still be used for the watchdog timer and for the reset time-out. for more information on the pre-programmed calibration value, see the section section ?calibration byte?, page 268 . table 6-4. start-up times for the o scillator clock selection cksel0 sut1..0 start-up time from power-down and power-save additional delay from reset (v cc = 5.0v) recommended usage 0 00 258 ck (1) 14ck + 4.1 ms ceramic resonator, fast rising power 0 01 258 ck (1) 14ck + 65 ms ceramic resonator, slowly rising power 010 1k ck (2) 14ck ceramic resonator, bod enabled 011 1k ck (2) 14ck + 4.1 ms ceramic resonator, fast rising power 100 1k ck (2) 14ck + 65 ms ceramic resonator, slowly rising power 1 01 16k ck 14ck crystal oscillator, bod enabled 1 10 16k ck 14ck + 4.1 ms crystal oscillator, fast rising power 1 11 16k ck 14ck + 65 ms crystal oscillator, slowly rising power table 6-5. internal calibrated rc o scillator operating modes (1)(2) frequency range (mhz) cksel3..0 7.3 - 8.1 0010 29 at90pwm216/316 [datasheet] 7710h?avr?07/2013 notes: 1. the device is shipped with this option selected. 2. if 8 mhz frequency exceeds the specification of the device (depends on v cc ), the ckdiv8 fuse can be pro- grammed in order to divide the internal frequency by 8. when this oscillator is selected , start-up times are determined by the sut fuses as shown in table 6-6 on page 29 . note: 1. if the rstdisbl fuse is programmed, this start-up time will be increased to 14ck + 4.1 ms to ensure programming mode can be entered. 2. the device is shipped with this option selected. 6.5.1 oscillator calibra tion register ? osccal ? bits 7..0 ? cal7..0: oscillator calibration value the oscillator calibration register is used to trim the calibrated internal rc oscillator to remove process varia- tions from the oscillator frequency. the factory-calibrated va lue is automatically written to this register during chip reset, giving an oscilla tor frequency of 8.0 mhz at 25c. the applicati on software can write this register to change the oscillator freque ncy. the oscillator can be calib rated to any frequency in the ra nge 7.3 - 8.1 mhz within 1% accuracy. calibration outside that range is not guaranteed. note that this oscillator is used to time eeprom and flash write accesses, and these write times will be affected accordingly. if the eeprom or flash are written, do not calibrate to more than 8.8 mhz. otherwise, the eeprom or flash write may fail. the cal7 bit determines the range of op eration for the oscillator. setting this bit to 0 gives the lowest frequency range, setting this bit to 1 gives the highest frequency range. the two frequency ranges are overlapping, in other words a setting of osccal = 0x7f gives a higher frequency than osccal = 0x80. the cal6..0 bits are used to tune the frequency within t he selected range. a setting of 0x00 gives the lowest fre- quency in that range, and a setting of 0x7f gives the highest frequency in the range. incrementing cal6..0 by 1 will give a frequency increment of less than 2% in the fr equency range 7.3 - 8.1 mhz. 6.6 pll to generate high frequency and accurate pwm waveforms, the ?psc?s need high frequency clock input. this clock is generated by a pll. to keep all pwm accuracy, the freq uency factor of pll must be configurable by software. with a system clock of 8 mhz, the pll output is 32mhz or 64mhz. table 6-6. start-up times for the internal calib rated rc oscillator clock selection power conditions start-up time from power- down and power-save additional delay from reset (v cc = 5.0v) sut1..0 bod enabled 6 ck 14ck (1) 00 fast rising power 6 ck 14ck + 4.1 ms 01 slowly rising power 6 ck 14ck + 65 ms (1) 10 reserved 11 bit 76543210 cal7 cal6 cal5 cal4 cal3 cal2 cal1 cal0 osccal read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value device specific calibration value 30 at90pwm216/316 [datasheet] 7710h?avr?07/2013 6.6.1 internal pll for psc the internal pll in at90pwm216/316 generates a clock fr equency that is 64x multip lied from nominally 1 mhz input. the source of the 1 mhz pll input clock is the output of the internal rc oscillat or which is divided down to 1 mhz. see the figure 6-4 on page 32 . the pll is locked on the rc oscillator and adjusting the rc oscillator via osccal register will adjust the fast peripheral clock at the same time. however, even if the possibly divided rc os cillator is taken to a higher fre- quency than 1 mhz, the fast periphera l clock frequency saturates at 70 mhz (worst case) and re mains oscillating at the maximum frequency. it shou ld be noted that the pll in this case is not locked an y more with the rc oscillator clock. therefore it is recommended not to take the osccal adjustments to a higher frequency than 1 mhz in order to keep the pll in the correct operating range. the internal pll is enabled only when the plle bit in the register pllcsr is set. the bit plock from the regi ster pllcsr is set when pll is locked. both internal 1 mhz rc oscillator and pll are sw itched off in power-dow n and standby sleep modes . table 6-7. start-up times when the pll is selected as system clock cksel 3..0 sut1..0 start-up time from power-down and power-save additional delay from reset (v cc = 5.0v) 0011 rc osc 00 1k ck 14ck 01 1k ck 14ck + 4 ms 10 1k ck 14ck + 64 ms 11 16k ck 14ck 0101 ext osc 00 1k ck 14ck 01 1k ck 14ck + 4 ms 10 16k ck 14ck + 4 ms 11 16k ck 14ck + 64 ms 0001 ext clk 00 6 ck (1) 1. this value do not provide a proper restart ; do not use pd in this clock scheme 14ck 01 6 ck (2) 2. this value do not provide a proper restart ; do not use pd in this clock scheme 14ck + 4 ms 10 6 ck (3) 3. this value do not provide a proper restart ; do not use pd in this clock scheme 14ck + 64 ms 11 reserved 31 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 6-3. pck clocking system at90pwm216/316 6.6.2 pll control and status register ? pllcsr ? bit 7..3 ? res: reserved bits these bits are reserved bits in the at90pwm216/316 and always read as zero. ? bit 2 ? pllf: pll factor the pllf bit is used to select the division factor of the pll. if pllf is set, the pll output is 64mhz. if pllf is clear, the pll output is 32mhz. ? bit 1 ? plle: pll enable when the plle is set, the pll is started and if not yet star ted the internal rc oscillator is started as pll reference clock. if pll is selected as a system clo ck source the value for this bit is always 1. ? bit 0 ? plock: pll lock detector when the plock bit is set, the pll is locked to th e reference clock, and it is safe to enable clk pll for psc. after the pll is enabled, it takes about 100 ms for the pll to lock. 6.7 128 khz internal oscillator the 128 khz internal oscillato r is a low power oscillator providing a cloc k of 128 khz. the fr equency is nominal at 3v and 25 ? c. this clock is used by the watchdog oscillator. 6.8 external clock to drive the device from an external cloc k source, xtal1 should be driven as shown in figure 6-4 . to run the device on an external cl ock, the cksel fuses must be programmed to ?0000?. 8 mhz rc oscillator osccal xtal1 xtal2 oscillators di v ide by 8 di v ide by 2 ck pll 64x plle lock detector plock source pllf di v ide by 4 clk pll cksel3..0 bit 76543210 $29 ($29) ?????pllfplleplockpllcsr read/write r r r r r r/w r/w r initial value0000000/10 32 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 6-4. external clock drive configuration when this clock source is selected, start-up times are determined by the sut fuses as shown in table 6-9 . when applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the mcu. a variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. it is required to ensure that the mcu is kept in reset during such changes in the clock frequency. note that the system clock prescaler can be used to im plement run-time changes of the internal clock frequency while still ensuring stabl e operation. refer to ?system clock prescaler? on page 32 for details. 6.9 clock output buffer when the ckout fuse is programmed, the system clock will be output on cl ko. this mode is suitable when chip clock is used to drive othe r circuits on the system. the clock will be outpu t also during reset and the normal opera- tion of i/o pin will be overridden when the fuse is programmed. any clock s ource, including internal rc oscillator, can be selected when clko serves as clock output. if the system clock prescaler is used, it is the divided system clock that is output (ckout fuse programmed). 6.10 system clock prescaler the at90pwm216/316 system clock can be divided by setting the clock presca le register ? clkpr. this feature can be used to decrease power consumption when the requi rement for processing power is low. this can be used with all clock source option s, and it will affect the cl ock frequency of the cpu and all synchr onous peripherals. clk i/o , clk adc , clk cpu , and clk flash are divided by a factor as shown in table 6-10 . when switching between prescaler settings, the system clock prescaler ensures that no glitches occurs in the clock system. it also ensures that no intermediate frequency is higher than neither the clock frequency correspond- ing to the previous setting, nor the clock frequency corresponding to the new setting. the ripple counter that implements the prescaler runs at the frequency of the undivided clock, whic h may be faster than the cpu's clock table 6-8. external clock frequency cksel3..0 frequency range 0000 0 - 16 mhz table 6-9. start-up times for the external clock selection sut1..0 start-up time from power- down and power-save additional delay from reset (v cc = 5.0v) recommended usage 00 6 ck 14ck bod enabled 01 6 ck 14ck + 4.1 ms fast rising power 10 6 ck 14ck + 65 ms slowly rising power 11 reserved xtal2 xtal1 gnd nc external clock signal 33 at90pwm216/316 [datasheet] 7710h?avr?07/2013 frequency. hence, it is not possible to determine the state of the prescaler - even if it we re readable, and the exact time it takes to switch from one cloc k division to the other cannot be exactly predicted. from the time the clkps values are written, it takes between t1 + t2 and t1 + 2 * t2 before the new clock frequency is active. in this inter- val, 2 active clock edges are produced. here, t1 is the pr evious clock period, and t2 is the period corresponding to the new prescaler setting. to avoid unintentional changes of clock frequency, a special write proced ure must be followed to change the clkps bits: 1. write the clock prescaler change enable (clkpce) bi t to one and all other bits in clkpr to zero. 2. within four cycles, write the desired value to clkps while writing a zero to clkpce. interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted. 6.10.1 clock prescaler register ? clkpr ? bit 7 ? clkpce: clock prescaler change enable the clkpce bit must be writ ten to logic one to enable change of the clkps bits . the clkpce bit is only updated when the other bits in clkpr are simultaneously written to zero. clkpce is cleared by hardware four cycles after it is written or when clkps bits are written. rewriti ng the clkpce bit within this time-out period does neither extend the time-out period, nor clear the clkpce bit. ? bits 3..0 ? clkps3..0: clock prescaler select bits 3 - 0 these bits define the division factor between the selected clock source and the internal system clock. these bits can be written run-time to vary the clock frequency to suit the application requirements. as the divider divides the master clock input to the mcu, the speed of all synchro nous peripherals is reduced when a division factor is used. the division factors are given in table 6-10 . the ckdiv8 fuse determines the initial value of the clkps bits. if ckdiv8 is unprogrammed, t he clkps bits will be reset to ?0000?. if ckdiv8 is progra mmed, clkps bits are reset to ?0011?, gi ving a division factor of 8 at start up. this feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. note that any value can be written to the clkps bits regardless of the ckdiv8 fuse sett ing. the application software mu st ensure that a sufficient di vision factor is chosen if the selected clock source has a higher frequency than the ma ximum frequency of the device at the present operating conditions. the device is shipped with the ckdiv8 fuse programmed. bit 76543210 clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 clkpr read/write r/w r r r r/w r/w r/w r/w initial value 0 0 0 0 see bit description table 6-10. clock prescaler select clkps3 clkps2 clkps1 clkps0 clock division factor 0000 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 34 at90pwm216/316 [datasheet] 7710h?avr?07/2013 0111 128 1000 256 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved table 6-10. clock prescaler select clkps3 clkps2 clkps1 clkps0 clock division factor 35 at90pwm216/316 [datasheet] 7710h?avr?07/2013 7. power management and sleep modes sleep modes enable the application to shut down unused modules in the mcu, thereby saving power. the avr provides various sleep modes allowing the user to tailor the power consumption to the application?s requirements. to enter any of the five sleep modes, the se bit in smcr must be written to logic one and a sleep instruction must be executed. the sm2, sm1, and sm0 bits in the sm cr register select which sleep mode (idle, adc noise reduction, power-down, power-save, or standby) will be activa ted by the sleep instruction. see table 7-1 for a summary. if an enabled interrupt occurs while the mcu is in a sleep mode, the mcu wakes up. the mcu is then halted for four cycles in addition to the start-up time, executes the interr upt routine, and resumes execution from the instruction following sleep. the contents of the register file and sram are unalte red when the device wakes up from sleep. if a reset occurs during sleep mode, the mcu wakes up and executes from the reset vector. figure 6-1 on page 25 presents the different clock systems in the at90pwm216/316, and their distribution. the figure is helpful in selecting an appropriate sleep mode. 7.0.1 sleep mode control register ? smcr the sleep mode control register contai ns control bits for power management. ? bits 3..1 ? sm2..0: sleep mode select bits 2, 1, and 0 these bits select between the five available sleep modes as shown in table 7-1 . note: 1. standby mode is only recommended for use with external crystals or resonators. ? bit 1 ? se: sleep enable the se bit must be written to logic one to make the mcu ente r the sleep mode when the sleep instruction is exe- cuted. to avoid the mcu entering the sleep mode unless it is the programmer?s purpose, it is recommended to write the sleep enable ( se) bit to one just before the execution of the sleep instructio n and to clear it immediately after waking up. 7.1 idle mode when the sm2..0 bits are written to 000, the sleep in struction makes the mcu enter idle mode, stopping the cpu but allowing spi, usart, analog comparator, adc, timer/ counters, watchdog, and the interrupt system to con- tinue operating. this sleep mode basically halt clk cpu and clk flash , while allowing the ot her clocks to run. bit 76543210 ? ? ? ? sm2 sm1 sm0 se smcr read/write rrrrr/wr/wr/wr/w initial value 00000000 table 7-1. sleep mode select sm2 sm1 sm0 sleep mode 000idle 0 0 1 adc noise reduction 010power-down 011reserved 100reserved 101reserved 110standby (1) 111reserved 36 at90pwm216/316 [datasheet] 7710h?avr?07/2013 idle mode enables the mcu to wake up from external triggered interrupts as well as internal ones like the timer overflow and usart transmit complete interrupts. if the adc is enabled, a conversion starts automatically when this mode is entered. 7.2 adc noise reduction mode when the sm2..0 bits are written to 001, the sleep instructio n makes the mcu enter a dc noise reduction mode, stopping the cpu but allowing the adc, the external interrupt s, timer/counter (if their clock source is external - t0 or t1) and the watchdog to continue operating (i f enabled). this sleep mode basically halts clk i/o , clk cpu , and clk flash , while allowing the ot her clocks to run. this improves the noise environment for the adc, enabling higher resolution measurements. if the adc is enabled, a conversion starts automatical ly when this mode is entered. apart from the adc conversion complete interrupt, only an external reset, a watchdog reset, a brown-out reset, a timer/counter interrupt, an spm/eeprom ready interrupt, an external level interr upt on int3:0 can wake up the mcu from adc noise reduction mode. 7.3 power-down mode when the sm2..0 bits are written to 010, the sleep instruction makes the mcu enter power-down mode. in this mode, the external osc illator is stopped, while the ex ternal interrupts and the wa tchdog continue operating (if enabled). only an external reset, a watchdog reset, a br own-out reset, a psc interrupt, an external level inter- rupt on int3:0 can wake up the mcu. this sleep mode bas ically halts all generated clocks, allowing operation of asynchronous modules only. note that if a level trigger ed interrupt is used for wake -up from power-down mode, the changed level must be held for some time to wake up the mcu. refer to ?external interrupts? on page 75 for details. when waking up from power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. this allows the clock to restart and become stable after having been stopped. the wake-up period is defined by the same c ksel fuses that define the reset ti me-out period, as described in ?clock sources? on page 26 . 7.4 standby mode when the sm2..0 bits are 110 and an external crystal/r esonator clock option is selected, the sleep instruction makes the mcu enter sta ndby mode. this mode is identi cal to power-down with the e xception that th e oscillator is kept running. from standby mode, the device wakes up in six clock cycles. notes: 1. only recommended with external crystal or resonator selected as clock source. 2. only level interrupt. table 7-2. active clock domains and wake-up sour ces in the different sleep modes. active clock domains oscillators wake-up sources sleep mode clk cpu clk flash clk io clk adc clk pll main clock source enabled int3..0 psc spm/eeprom ready adc wdt otheri/o idle xxx x x x x xxx adc noise reduction x x x x (2) xxxx power-down x (2) xx standby (1) xx (2) x 37 at90pwm216/316 [datasheet] 7710h?avr?07/2013 7.5 power reduction register the power reduction register, pr r, provides a method to stop the clock to individual peripherals to reduce power consumption. the current st ate of the peripheral is frozen and the i/o registers can not be read or written. resources used by the peripheral w hen stopping the clock will remain oc cupied, hence the per ipheral should in most cases be disabled before stopping the clock. waking up a module, which is done by clearing the bit in prr, puts the module in the same state as before shutdown. a full predictable behavior of a peripheral is not guaranteed during and after a cycle of stopping and starting of its clock. so its recommended to stop a peripheral before stopping its clock with prr register. module shutdown can be used in idle mode and active mode to significantly reduce the overall power consump- tion. in all other sleep modes, the clock is already stopped. 7.5.1 power reduction register - prr ? bit 7 - prpsc2: power reduction psc2 writing a logic one to this bit reduces the consumption of the psc2 by stopping the clock to this module. when waking up the psc2 again, the psc2 should be re initialized to ensure proper operation. ? bit 6 - prpsc1: power reduction psc1 writing a logic one to this bit reduces the consumption of the psc1 by stopping the clock to this module. when waking up the psc1 again, the psc1 should be re initialized to ensure proper operation. ? bit 5 - prpsc0: power reduction psc0 writing a logic one to this bit reduces the consumption of the psc0 by stopping the clock to this module. when waking up the psc0 again, the psc0 should be re initialized to ensure proper operation. ? bit 4 - prtim1: power reduction timer/counter1 writing a logic one to this bit reduces the consumption of the timer/counter1 module. when the timer/counter1 is enabled, operation will co ntinue like before the setting of this bit. ? bit 3 - prtim0: power reduction timer/counter0 writing a logic one to this bit reduces the consumption of the timer/counter0 module. when the timer/counter0 is enabled, operation will co ntinue like before the setting of this bit. ? bit 2 - prspi: power reduction serial peripheral interface writing a logic one to this bit reduces the consumption of the serial peripheral interface by stopping the clock to this module. when waking up the spi again, the spi sh ould be re initialized to ensure proper operation. ? bit 1 - prusart0: power reduction usart0 writing a logic one to this bit reduces the consumption of the usart by stopping the clock to this module. when waking up the usart again, the usart should be re initialized to ensure proper operation. ? bit 0 - pradc: power reduction adc writing a logic one to this bit reduces the consumption of the adc by stopping the clock to this module. the adc must be disabled before using this function. the analog comparator canno t use the adc input mux when the clock of adc is stopped. bit 765432 1 0 prpsc2 prpsc1 prpsc0 prtim1 prtim0 prspi prusart pradc prr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 38 at90pwm216/316 [datasheet] 7710h?avr?07/2013 7.6 minimizing power consumption there are several issues to consider when trying to mini mize the power consumption in an avr controlled system. in general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device?s functi ons are operating. all functions not need ed should be disabled. in particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption. 7.6.1 analog to digital converter if enabled, the adc will be enab led in all sleep modes. to save power, the adc should be di sabled before entering any sleep mode. when the adc is turned off and on again, the next conversi on will be an extended conversion. refer to ?cross reference remove d? for details on adc operation. 7.6.2 analog comparator when entering idle mode, the analog comparator should be disabled if not used. when entering adc noise reduction mode, the analog comparator should be disabled. in other sleep modes, the analog comparator is automatically disabled. however, if the analog comparator is set up to use the internal voltage reference as input, the analog comparator should be disabled in all sleep mo des. otherwise, the intern al voltage reference will be enabled, independent of sleep mode. refer to ?analog comparator? on page 215 for details on how to configure the analog comparator. 7.6.3 brown-out detector if the brown-out detector is not neede d by the application, this module s hould be turned off. if the brown-out detector is enabled by the bodlevel fuses, it will be enabled in all sleep modes, and hence, always consume power. in the deeper sleep modes, this will contribute significantly to the total current consumpt ion. refer to ?brown-out detection? on page 42 for details on how to conf igure the brown-out detector. 7.6.4 internal voltage reference the internal voltage refere nce will be enabled when need ed by the brown-out detect ion, the anal og comparator or the adc. if these modules are disabled as described in the sections above, the internal vo ltage reference will be disabled and it will not be consuming power. when turned on again , the user must allow t he reference to start up before the output is used. if the reference is kept on in sleep mode, the output can be used immediately. refer to ?internal voltage reference? on page 44 for details on the start-up time. 7.6.5 watchdog timer if the watchdog timer is not needed in the application, the module should be turned off. if the watchdog timer is enabled, it will be enabled in all sleep modes, and hence, always cons ume power. in the dee per sleep modes, this will contribute significantly to the total current consumption. refer to ?watchdog timer? on page 45 for details on how to configure the watchdog timer. 7.6.6 port pins when entering a sleep mode, all port pins should be config ured to use minimum power. the most important is then to ensure that no pins drive resistive load s. in sleep modes where both the i/o clock (clk i/o ) and the adc clock (clk adc ) are stopped, the input buffers of the device will be disabled. this ensures that no power is consumed by the input logic when not needed. in some cases, the inpu t logic is needed for detecting wake-up conditions, and it will then be enabled. refer to the section ?i/o-ports? on page 56 for details on which pins are enabled. if the input buffer is enabled and the i nput signal is left floating or hav e an analog signal level close to v cc /2, the input buffer will use excessive power. for analog input pins, the digital input buffer should be di sabled at all times. an analog signal level close to v cc /2 on an input pin can cause significant current even in active mode. digital input buffers ca n be disabled by writing to 39 at90pwm216/316 [datasheet] 7710h?avr?07/2013 the digital input disable registers (d idr1 and didr0). refer to ?digital input disable register 1? didr1? and ?digital input disable register 0 ? didr0? on page 221 and page 239 for details. 7.6.7 on-chip debug system if the on-chip debug system is enabled by ocden fuse and the chip enter sleep mode, the main clock source is enabled, and hence, always consumes power. in the deeper sleep modes, this will cont ribute significantly to the total current consumption. 40 at90pwm216/316 [datasheet] 7710h?avr?07/2013 8. system control and reset 8.1 resetting the avr during reset, all i/o registers are set to their initial values, and the program starts execution from the reset vec- tor. the instruction placed at the reset vector must be a jmp ? absolute ju mp ? instruction to the reset handling routine. if the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these loca tions. this is also the case if the reset vector is in the application section while the interrupt vectors are in the boot section or vice versa. the circuit diagram in figure 8-1 shows the reset logic. table 8-1 defines the electrical parame ters of the reset circuitry. the i/o ports of the avr are immediately reset to their initial state when a rese t source goes active. this does not require any clock source to be running. after all reset sources have gone inactive, a delay counter is invoked, stretching the inte rnal reset. this allows the power to reach a stable level before normal operation starts . the time-out period of the delay counter is defined by the user through the sut and cksel fuses. the different selections for the delay period are presented in ?clock sources? on page 26 . 8.2 reset sources the at90pwm216/316 has four sources of reset: ? power-on reset. the mcu is reset when the supply voltage is below the power-on reset threshold (v pot ). ? external reset. the mcu is reset when a low level is pr esent on the reset pin for longer than the minimum pulse length. ? watchdog reset. the mcu is reset when the watchdog timer period expires and the watchdog is enabled. ? brown-out reset. the mcu is reset when the supply voltage v cc is below the brown-out reset threshold (v bot ) and the brown-out detector is enabled. figure 8-1. reset logic mcu status register (mcusr) brown-out reset circuit bodle v el [2..0] delay counters cksel[3:0] ck timeout wdrf borf extrf porf data b u s clock generator spike filter pull-up resistor watchdog oscillator sut[1:0] power-on reset circuit 41 at90pwm216/316 [datasheet] 7710h?avr?07/2013 notes: 1. values are guidelines only. 2. the power-on reset will not work unless the supply voltage has been below v pot (falling). 8.3 power-on reset a power-on reset (por) pulse is generated by an on-chi p detection circuit. the detection level is defined in table 8-1 . the por is activated whenever v cc is below the detection level. the por circuit can be used to trigger the start-up reset, as well as to dete ct a failure in supply voltage. a power-on reset (por) circuit ensures that the device is reset from power-on. reaching the power-on reset threshold voltage invokes the delay co unter, which determines ho w long the device is kept in reset after v cc rise. the reset signal is activated ag ain, without any delay, when v cc decreases below the detection level. figure 8-2. mcu start-up, reset tied to v cc figure 8-3. mcu start-up, reset extended externally table 8-1. reset characteristics (1) symbol parameter condition min. typ. max. units v pot power-on reset threshold voltage (rising) 1.4 2.3 v power-on reset threshold voltage (falling) (2) 1.3 2.3 v v rst reset pin threshold voltage 0.2vcc 0.85vcc v t rst minimum pulse width on reset pin 400 ns v por v cc start voltage to ensure internal power-on reset signal -0.05 gnd +0.05 v v ccrr v cc rise rate to ensure internal power-on reset signal 0.3 v/ms v reset time-out internal reset t tout v pot v rst cc reset time-out internal reset t tout v pot v rst v cc 42 at90pwm216/316 [datasheet] 7710h?avr?07/2013 8.4 external reset an external reset is generated by a lo w level on the reset pin. reset pulses longer than the minimum pulse width (see table 8-1 ) will generate a reset, even if the clock is not running. shorter pulses are not guaranteed to generate a reset. when the applied signal reaches the reset threshold voltage ? v rst ? on its positive edge, the delay counter starts the mcu after the time-out period ? t tout ? has expired. figure 8-4. external reset during operation 8.5 brown-out detection at90pwm216/316 has an on-chip brown-out de tection (bod) circuit for monitoring the v cc level during operation by comparing it to a fixed trigger level. the trigger leve l for the bod can be selected by the bodlevel fuses. the trigger level has a hysteresis to ensure spike free br own-out detection. the hysteresis on the detection level should be interpreted as v bot+ = v bot + v hyst /2 and v bot- = v bot - v hyst /2. notes: 1. v bot may be below nominal minimum operating voltage for some devices. for devices where this is the case, the device is tested down to v cc = v bot during the production test. this guarantees that a brown-out reset will occur before v cc drops to a voltage where correct operation of the micr ocontroller is no longer guaranteed. the test is performed using bodlevel = 010 for low operating volt age and bodlevel = 101 for high operating voltage . 2. values are guidelines only. cc table 8-2. bodlevel fuse coding (1)(2) bodlevel 2..0 fuses min v bot typ v bot max v bot units 111 bod disabled 110 4.5 v 101 2.5 2.7 2.9 v 100 4.3 v 011 4.4 v 010 4 4.2 4.4 v 001 2.8 v 000 2.6 v 43 at90pwm216/316 [datasheet] 7710h?avr?07/2013 notes: 1. values are guidelines only. when the bod is enabled, and v cc decreases to a value below the trigger level (v bot- in figure 8-5 ), the brown- out reset is immediately activated. when v cc increases above the trigger level (v bot+ in figure 8-5 ), the delay counter starts the mcu after the time-out period t tout has expired. the bod circuit will only detect a drop in v cc if the voltage stays below the trigger level for longer than t bod given in table 8-3 . figure 8-5. brown-out reset during operation 8.6 watchdog reset when the watchdog times out, it will gen erate a short reset pulse of one ck cycle duration. on the falling edge of this pulse, the delay timer star ts counting the time-out period t tout . refer to page 45 for details on operation of the watchdog timer. figure 8-6. watchdog reset during operation table 8-3. brown-out characteristics (1) symbol parameter min. typ. max. units v hyst brown-out detector hysteresis 70 mv t bod min pulse width on brown-out reset 2 s v cc reset time-out internal reset v bot- v bot+ t tout ck cc 44 at90pwm216/316 [datasheet] 7710h?avr?07/2013 8.7 mcu status re gister ? mcusr the mcu status register prov ides information on which reset source caused an mcu reset. ? bit 3 ? wdrf: watchdog reset flag this bit is set if a watchdog reset occurs. the bit is reset by a power-on reset, or by writing a logic zero to the flag. ? bit 2 ? borf: brown-out reset flag this bit is set if a brown-out reset occurs. the bit is re set by a power-on reset, or by writing a logic zero to the flag. ? bit 1 ? extrf: external reset flag this bit is set if an external reset occurs. the bit is reset by a power-on reset, or by writing a logic zero to the flag. ? bit 0 ? porf: power-on reset flag this bit is set if a power-on reset occurs. the bit is reset only by writing a logic zero to the flag. to make use of the reset flags to identify a reset cond ition, the user should read and then reset the mcusr as early as possible in the program. if the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags. 8.8 internal voltage reference at90pwm216/316 features an internal bandgap reference. this reference is used for brown-out detection. the v ref 2.56v reference to the adc, dac or analog comparators is generated from the internal bandgap reference. in order to use the internal vref, it is necessary to conf igure it thanks to the refs1 and refs0 bits in the admux register and to set an analog feature which requires it. 8.8.1 voltage reference enable signals and start-up time the voltage reference has a start-up time that may influenc e the way it should be used. the start-up time is given in table 8-4 . to save power, the reference is not always turned on. the reference is on during the following situations: 1. when the bod is enabled (by prog ramming the bodlevel [2..0] fuse). 2. when the adc is enabled. 3. when the dac is enabled. thus, when the bod is not enabled, after enabling the adc or the dac, the user must always allow the reference to start up before the output from the analog comparator or adc or dac is used. to reduce power consumption in power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering power-down mode. bit 76543210 ? ? ? ? wdrf borf extrf porf mcusr read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 see bit description 45 at90pwm216/316 [datasheet] 7710h?avr?07/2013 8.8.2 voltage reference characteristics note: 1. values are guidelines only. 8.9 watchdog timer at90pwm216/316 has an enhanced watchdog timer (wdt). the main features are: ? clocked from separate on-chip oscillator ? 3 operating modes ?interrupt ? system reset ? interrupt and system reset ? selectable time-out period from 16ms to 8s ? possible hardware fuse watchdog al ways on (wdton) for fail-safe mode figure 8-7. watchdog timer the watchdog timer (wdt) is a timer counting cycles of a separate on-chip 128 khz oscillator. the wdt gives an interrupt or a system reset when the counter reaches a given time-out valu e. in normal operation mode, it is required that the system uses the wdr - watchdog timer reset - instructi on to restart the counter before the time- out value is reached. if th e system doesn't restart the counter, an interrupt or system reset will be issued. in interrupt mode, the wdt gives an interrupt when the ti mer expires. this interrupt can be used to wake the device from sleep-modes, and also as a general system ti mer. one example is to limit the maximum time allowed for certain operations, giving an interrupt when the operat ion has run longer than expected. in system reset mode, the wdt gives a reset when the timer expires. this is typically used to prevent system hang-up in case of runaway code. the third mode, interrupt and syst em reset mode, combines the other two modes by first giving an interrupt table 8-4. internal voltage reference characteristics (1) symbol parameter condition min. typ. max. units v bg bandgap reference voltage 1.1 v t bg bandgap reference start-up time 40 s i bg bandgap reference current consumption 15 a 12 8 khz oscillator mcu reset i n terrupt wdie wdif osc/2k osc/4k osc/ 8 k wdp3 46 at90pwm216/316 [datasheet] 7710h?avr?07/2013 and then switch to system re set mode. this mode will for in stance allow a safe shutdown by saving critical param- eters before a system reset. the ?watchdog timer always on? (wdt on) fuse, if programmed, will force t he watchdog timer to system reset mode. with the fuse programmed the system reset mode bit (wde) and interrupt mode bit (wdie) are locked to 1 and 0 respectively. to further ensure program security, alterations to the watchdog set-up must follow timed sequences. the sequence for clearing wde and ch anging time-out configur ation is as follows: 1. in the same operation, write a logic one to the watchdog change enable bit (wdce) and wde. a logic one must be written to wde regardless of the previous value of the wde bit. 2. within the next four clock cycles, write the wde and watchdog prescaler bits (wdp) as desired, but with the wdce bit cleared. this must be done in one operation. the following code example shows one assembly and one c function for turning off the watchdog timer. the example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of these functions. 47 at90pwm216/316 [datasheet] 7710h?avr?07/2013 note: 1. the example code assumes that the part specific header file is included. note: if the watchdog is accidentally enabled, for exampl e by a runaway pointer or brown-out condition, the device will be reset and the watchdog timer will stay enabled. if the co de is not set up to handle the watchdog, this might lead to an eternal loop of time-out resets. to avoid this situation, the application softw are should always clear the watchdog system reset flag (wdrf) and the wde control bit in the initialisati on routine, even if the watchdog is not in use. the following code example shows one assembly and one c fu nction for changing the time-out value of the watch- dog timer. table 2. assembly code example (1) wdt_off: ; turn off global interrupt cli ; reset watchdog timer wdr ; clear wdrf in mcusr in r16, mcusr andi r16, (0xff & (0< 50 at90pwm216/316 [datasheet] 7710h?avr?07/2013 . table 8-6. watchdog timer prescale select wdp3 wdp2 wdp1 wdp0 number of wdt oscillator cycles typical time-out at v cc = 5.0v 0 0 0 0 2k (2048) cycles 16 ms 0 0 0 1 4k (4096) cycles 32 ms 0 0 1 0 8k (8192) cycles 64 ms 0 0 1 1 16k (16384 ) cycles 0.125 s 0 1 0 0 32k (32768) cycles 0.25 s 0 1 0 1 64k (65536) cycles 0.5 s 0 1 1 0 128k (131072) cycles 1.0 s 0 1 1 1 256k (262144) cycles 2.0 s 1 0 0 0 512k (524288) cycles 4.0 s 1 0 0 1 1024k (1048576) cycles 8.0 s 1010 reserved 1011 1100 1101 1110 1111 51 at90pwm216/316 [datasheet] 7710h?avr?07/2013 9. interrupts this section describes the specifics of the interrupt handling as performed in at90pwm216/316. for a general explanation of the avr interrupt handling, refer to ?reset and interrupt handling? on page 15 . 9.1 interrupt vectors in at90pwm216/316 table 9-1. reset and interrupt vectors vector no. program address source interrupt definition 1 0x0000 reset external pin, power-on reset, brown-out reset, watchdog reset, and emulation avr reset 2 0x0002 psc2 capt psc2 capture event 3 0x0004 psc2 ec psc2 end cycle 4 0x0006 psc1 capt psc1 capture event 5 0x0008 psc1 ec psc1 end cycle 6 0x000a psc0 capt psc0 capture event 7 0x000c psc0 ec psc0 end cycle 8 0x000e anacomp 0 analog comparator 0 9 0x0010 anacomp 1 analog comparator 1 10 0x0012 anacomp 2 analog comparator 2 11 0x0014 int0 external interrupt request 0 12 0x0016 timer1 capt timer/counter1 capture event 13 0x0018 timer1 compa timer/counter1 compare match a 14 0x001a timer1 compb timer/counter1 compare match b 15 0x001c 16 0x001e timer1 ovf timer/counter1 overflow 17 0x0020 timer0 compa timer/counter0 compare match a 18 0x0022 timer0 ovf timer/counter0 overflow 19 0x0024 adc adc conversion complete 20 0x0026 int1 external interrupt request 1 21 0x0028 spi, stc spi se rial transfer complete 22 0x002a usart0, rx usart0, rx complete 23 0x002c usart0, udre usart0 data register empty 24 0x002e usart0, tx usart0, tx complete 25 0x0030 int2 external interrupt request 2 26 0x0032 wdt watchdog time-out interrupt 27 0x0034 ee ready eeprom ready 28 0x0036 timer0 compb timer/counter0 compare match b 29 0x0038 int3 external interrupt request 3 52 at90pwm216/316 [datasheet] 7710h?avr?07/2013 notes: 1. when the bootrst fuse is programmed, the device will jump to the boot loader address at reset, see ?boot loader support ? read-while-write self-programming? on page 251 . 2. when the ivsel bit in mcucr is set, interrupt vectors wil l be moved to the start of the boot flash section. the address of each interrupt vector will then be the address in th is table added to the start address of the boot flash section. table 9-2 shows reset and interrup t vectors placement for the various co mbinations of boot rst and ivsel set- tings. if the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these loca tions. this is also the case if the reset vector is in the application section while the interrupt ve ctors are in the boot section or vice versa. note: 1. the boot reset address is shown in table 23-6 on page 263 . for the bootrst fuse ?1? means unprogrammed while ?0? means programmed. the most typical and general program setup for the reset and interrupt vector addresses in at90pwm216/316 is: address labels code comments 0x000 rjmp reset ; reset handler 0x002 rjmp psc2_capt ; psc2 capture event handler 0x004 rjmp psc2_ec ; psc2 end cycle handler 0x006 rjmp psc1_capt ; psc1 capture event handler 0x008 rjmp psc1_ec ; psc1 end cycle handler 0x00a rjmp psc0_capt ; psc0 capture event handler 0x00c rjmp psc0_ec ; psc0 end cycle handler 0x00e rjmp ana_comp_0 ; analog comparator 0 handler 0x010 rjmp ana_comp_1 ; analog comparator 1 handler 0x012 rjmp ana_comp_2 ; analog comparator 2 handler 0x014 rjmp ext_int0 ; irq0 handler 0x016 rjmp tim1_capt ; timer1 capture handler 0x01a rjmp tim1_compa ; timer1 compare a handler 0x01c rjmp tim1_compb ; timer1 compare b handler 0x01e rjmp tim1_ovf ; timer1 overflow handler 0x020 rjmp tim0_compa ; timer0 compare a handler 0x022 rjmp tim0_ovf ; timer0 overflow handler 0x024 rjmp adc ; adc conversion complete handler 0x026 rjmp ext_int1 ; irq1 handler 30 0x003a 31 0x003c 32 0x003e spm ready store program memory ready table 9-2. reset and interrupt vectors placement in at90pwm216/316 (1) bootrst ivsel reset address inter rupt vectors start address 1 0 0x000 0x001 1 1 0x000 boot reset address + 0x001 0 0 boot reset address 0x001 0 1 boot reset address boot reset address + 0x001 table 9-1. reset and interrupt vectors vector no. program address source interrupt definition 53 at90pwm216/316 [datasheet] 7710h?avr?07/2013 0x028 rjmp spi_stc ; spi transfer complete handler 0x02a rjmp usart_rxc ; usart, rx complete handler 0x02c rjmp usart_udre ; usart, udr empty handler 0x02e rjmp usart_txc ; usart, tx complete handler 0x030 rjmp ext_int2 ; irq2 handler 0x032 rjmp wdt ; watchdog timer handler 0x034 rjmp ee_rdy ; eeprom ready handler 0x036 rjmp tim0_compb ; timer0 compare b handler 0x038 rjmp ext_int3 ; irq3 handler 0x03e rjmp spm_rdy ; store program memory ready handler ; 0x040reset: ldi r16, high(ramend); main program start 0x041 out sph,r16 ; set stack pointer to top of ram 0x042 ldi r16, low(ramend) 0x043 out spl,r16 0x044 sei ; enable interrupts 0x045 54 at90pwm216/316 [datasheet] 7710h?avr?07/2013 0xc03 out spl,r16 0xc04 sei ; enable interrupts 0xc05 55 at90pwm216/316 [datasheet] 7710h?avr?07/2013 ? bit 0 ? ivce: interrupt vector change enable the ivce bit must be written to logi c one to enable change of the ivsel bi t. ivce is cleared by hardware four cycles after it is written or when ivsel is written. settin g the ivce bit will disable in terrupts, as explained in the ivsel description above. see code example below. table 2. assembly code example move_interrupts: ; enable change of interrupt vectors ldi r16, (1< 57 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 10-2. general digital i/o (1) note: 1. wrx, wpx, wdx, rrx, rpx, and rdx are common to all pins wit hin the same port. clk i/o , sleep, and pud are common to all ports. 10.2.1 configuring the pin each port pin consists of three register bits: ddxn, portxn, and pinxn. as shown in ?register description for i/o- ports? on page 73 , the ddxn bits are accessed at the ddrx i/o address, the portxn bits at the portx i/o address, and the pinxn bits at the pinx i/o address. the ddxn bit in the ddrx register select s the direction of this pin. if ddxn is written logic one, pxn is configured as an output pin. if ddxn is written logic zero, pxn is configured as an input pin. if portxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. to switch the pull-up resistor off, portxn has to be written logic ze ro or the pin has to be configured as an output pin the port pins are tri-stated when reset condition becomes active, even if no clocks are running. if portxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). if portxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 10.2.2 toggling the pin writing a logic one to pinxn toggles the value of portxn , independent on the value of ddrxn. note that the sbi instruction can be used to toggle one single bit in a port. clk rpx rrx rdx wdx pud sy n chro n izer wdx: write ddrx wrx: write portx rrx: read portx register rpx: read portx pi n pud: pullup disable clk i/o : i/o clock rdx: read ddrx d l q q reset reset q q d q q d clr portxn q q d clr ddxn pinxn data b u s sleep sleep: sleep co n trol pxn i/o wpx 0 1 wrx wpx: write pi n x register 58 at90pwm216/316 [datasheet] 7710h?avr?07/2013 10.2.3 switching between input and output when switching between tri-state ({ddxn, portxn} = 0b00 ) and output high ({ddxn, portxn} = 0b11), an inter- mediate state with either pull-up enabled {ddxn, portxn} = 0b01) or out put low ({ddxn, portxn} = 0b10) must occur. normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. if this is not the case, the pud bit in the mcucr register can be set to disable a ll pull-ups in all ports. switching between input with pull-up and output low generate s the same problem. the user must use either the tri- state ({ddxn, portxn} = 0b00) or the output high stat e ({ddxn, portxn} = 0b11) as an intermediate step. table 10-1 summarizes the control signals for the pin value. 10.2.4 reading the pin value independent of the setting of data direction bit ddxn, t he port pin can be read through the pinxn register bit. as shown in figure 10-2 , the pinxn register bit and the preceding latc h constitute a synchronizer. this is needed to avoid metastability if the physical pin changes value near t he edge of the internal clock, but it also introduces a delay. figure 10-3 shows a timing diagram of the synchronization when reading an externally applied pin value. the maximum and minimum propagation delays are denoted t pd,max and t pd,min respectively. figure 10-3. synchronization when reading an externally applied pin value consider the clock period starting shortly after the first falling edge of the system clock. the latch is closed when the clock is low, and goes transpar ent when the clock is high, as indicated by the sh aded region of the ?sync latch? signal. the signal value is latche d when the system clock goes low. it is clocked into the pinxn register at table 10-1. port pin configurations ddxn portxn pud (in mcucr) i/o pull-up comment 0 0 x input no default configuration after reset. tri-state (hi-z) 0 1 0 input yes pxn will source current if ext. pulled low. 0 1 1 input no tri-state (hi-z) 1 0 x output no output low (sink) 1 1 x output no output high (source) xxx in r17, pi n x 0x00 0xff i n structio n s sy n c latch pi n xn r17 xxx system clk t pd, max t pd, min 59 at90pwm216/316 [datasheet] 7710h?avr?07/2013 the succeeding positive clock edge. as indicated by the two arrows t pd,max and t pd,min , a single signal transition on the pin will be delayed between ? and 1? system cl ock period dependi ng upon the time of assertion. when reading back a software assigned pin value, a nop instruction must be inserted as indicated in figure 10-4 . the out instruction sets the ?sync lat ch? signal at the positive edge of th e clock. in this case, the delay t pd through the synchronizer is 1 system clock period. figure 10-4. synchronization when reading a software assigned pin value the following code example shows how to set port b pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. the resulting pin values are read back again, but as pre- viously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. out portx, r16 nop in r17, pinx 0xff 0x00 0xff system clk r16 instructions sync latch pinxn r17 t pd 60 at90pwm216/316 [datasheet] 7710h?avr?07/2013 note: 1. for the assembly program, two temporary registers are us ed to minimize the time from pull-ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defi ning bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers. 10.2.5 digital input enable and sleep modes as shown in figure 10-2 , the digital input signal can be clamped to gr ound at the input of the schmitt-trigger. the signal denoted sleep in the figure, is set by the mc u sleep controller in power- down mode, power-save mode, and standby mode to avoid high power consumption if some i nput signals are left floating, or have an analog signal level close to v cc /2. sleep is overridden for port pins enabled as external inte rrupt pins. if the external in terrupt request is not enabled, sleep is active also for these pins. sl eep is also overridden by various other alternate function s as described in ?alternate port functions? on page 61 . if a logic high level (?one?) is present on an asynchronous external interrupt pin configur ed as ?interrupt on rising edge, falling edge, or any logic change on pin? while the external interrupt is not enabled, the corresponding external interrupt flag will be set when resuming from the above mentioned sleep m odes, as the clamping in these sleep modes produces the requested logic change. assembly code example (1) ... ; define pull-ups and set outputs high ; define directions for port pins ldi r16, (1< 62 at90pwm216/316 [datasheet] 7710h?avr?07/2013 the following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. refer to the alternat e function description for further details. 10.3.1 mcu control register ? mcucr ? bit 4 ? pud: pull-up disable when this bit is written to one, the pull-ups in the i/o ports are disabled even if the ddxn and portxn registers are configured to enable the pull-ups ({ddxn, portxn} = 0b01). see ?configuring the pin? on page 57 for more details about this feature. table 10-2. generic description of overriding signals for alternate functions signal name full name description puoe pull-up override enable if this signal is set, the pull-up enable is controlled by the puov signal. if this signal is cleared, the pull-up is enabled when {ddxn, portxn, pud} = 0b010. puov pull-up override value if puoe is set, the pull-up is enabl ed/disabled when puov is set/cleared, regardless of the setting of the dd xn, portxn, and pud register bits. ddoe data direction override enable if this signal is set, the output driver en able is controlled by t he ddov signal. if this signal is cleared, the output driver is enabled by the ddxn register bit. ddov data direction override value if ddoe is set, the output driver is ena bled/disabled when ddov is set/cleared, regardless of the setting of the ddxn register bit. pvoe port value override enable if this signal is set and the output driver is enabled, the port value is controlled by the pvov signal. if pvoe is cleared, and the output driver is enabled, the port value is controlled by the portxn register bit. pvov port value override value if pvoe is set, the port value is set to pvov, regardless of the setting of the portxn register bit. ptoe port toggle override enable if ptoe is set, the portxn register bit is inverted. dieoe digital input enable override enable if this bit is set, the digital input enable is controlled by the dieov signal. if this signal is cleared, the digital input enable is determined by mcu state (normal mode, sleep mode). dieov digital input enable override value if dieoe is set, the digital input is enab led/disabled when dieov is set/cleared, regardless of the mcu state (normal mode, sleep mode). di digital input this is the digital input to alternate functions. in the fi gure, the signal is connected to the output of the schmitt trigger but before the synchronizer. unless the digital input is used as a clock source, the module with the alternate function will use its own synchronizer. aio analog input/output this is the analog input/output to/from alternate function s. the signal is connected directly to the pad, and c an be used bi-directionally. bit 7 6 5 4 3 2 1 0 spips ? ?pud ? ? ivsel ivce mcucr read/write r/w r r r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 63 at90pwm216/316 [datasheet] 7710h?avr?07/2013 10.3.2 alternate functions of port b the port b pins with alternate functions are shown in table 10-3 . the alternate pin configuration is as follows: ? pscout01/adc4/sck ? bit 7 pscout01: output 1 of psc 0. adc4, analog to digital converter, input channel 4 . sck: master clock output, slave cloc k input pin for spi channel. when the sp i is enabled as a slave, this pin is configured as an input regardless of the setting of ddb7 . when the spi is enabled as a master, the data direction of this pin is controlled by ddb7. when the pin is forced to be an i nput, the pull-up can still be controlled by the portb7 bit. ? adc7/icp1b/pscout11 ? bit 6 adc7, analog to digital converter, input channel 7 . icp1b, input capture pin: the pb6 pin can act as an input capture pin for timer/counter1. pscout11: output 1 of psc 1. ? adc6/int2 ? bit 5 adc6, analog to digital converter, input channel 6 . int2, external interrupt so urce 2. this pin can serve as an ex ternal interrupt so urce to the mcu. ? apm0+ ? bit 4 amp0+, analog differential amplifier 0 positive input channel. ? amp0- ? bit 3 amp0-, analog differential amplifier 0 negative input channel. table 10-3. port b pins alternate functions port pin alternate functions pb7 pscout01 output adc4 (analog input channel 4) sck (spi bus serial clock) pb6 adc7 (analog input channel 7) icp1b (timer 1 input capture alternate input) pscout11 output (see note 4) pb5 adc6 (analog input channel 6) int2 pb4 amp0+ (analog differential amplifier 0 input channel ) pb3 amp0- (analog differential amplifier 0 input channel ) pb2 adc5 (analog input channel5 ) int1 pb1 mosi (spi master out slave in) pscout21 output pb0 miso (spi master in slave out) pscout20 output 64 at90pwm216/316 [datasheet] 7710h?avr?07/2013 ? adc5/int1 ? bit 2 adc5, analog to digital converter, input channel 5 . int1, external interrupt so urce 1. this pin can serve as an external interrupt source to the mcu. ? mosi/pscout21 ? bit 1 mosi: spi master data output, slave data input for spi channel. when the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddb1 w hen the spi is enabled as a master, the data direction of this pin is controlled by ddb1. when the pin is forced to be an input, the pull-up ca n still be controlled by the portb1 and pud bits. pscout21: output 1 of psc 2. ? miso/psc20 ? bit 0 miso: master data input, slave data output pin for spi channel. when the spi is enabled as a master, this pin is configured as an input regardless of the setting of ddb0. when the spi is enabled as a slave, the data direction of this pin is controlled by ddb0. when the pin is forced to be an input, the pull-up ca n still be controlled by the portb0 and pud bits. pscout20: output 0 of psc 2. table 10-4 and table 10-5 relates the alternate functions of port b to the overriding signals shown in figure 10-5 on page 61 . table 10-4. overriding signals for alternate functions in pb7..pb4 signal name pb7/adc4/ pscout01/sck pb6/adc7/ pscout11/ icp1b pb5/adc6/ int2 pb4/amp0+ puoe spe ? mstr ? spips 000 puov pb7 ? pud ? spips 000 ddoe spe ? mstr ? spips + pscen01 pscen11 0 0 ddov pscen01 1 0 0 pvoe spe ? mstr ? spips pscen11 0 0 pvov pscout01 ? spips + pscout01 ? pscen01 ? spips + pscout01 ? pscen01 ? spips pscout11 0 0 dieoe adc4d adc7d adc6d + in2en amp0nd dieov 0 0 in2en 0 di sckin ? spips ? ireset icp1b int2 aio adc4 adc7 adc6 amp0+ 65 at90pwm216/316 [datasheet] 7710h?avr?07/2013 10.3.3 alternate functions of port c the port c pins with alternate functions are shown in table 10-6 . the alternate pin configuration is as follows: ? d2a ? bit 7 d2a, digital to analog output table 10-5. overriding signals for alternate functions in pb3..pb0 signal name pb3/amp0- pb2/adc5/int1 pb1/mosi/ pscout21 pb0/miso/ pscout20 puoe 0 0 ? ? puov 0 0 ? ? ddoe 0 0 ? ? ddov 0 0 ? ? pvoe 0 0 ? ? pvov 0 0 ? ? dieoe amp0nd adc5d + in1en 0 0 dieov 0 in1en 0 0 di int1 mosi_in ? spips ? ireset miso_in ? spips ? ireset aio amp0- adc5 ? ? table 10-6. port c pins alternate functions port pin alternate function pc7 d2a : dac output pc6 adc10 (analog input channel 10) acmp1 (analog comparator 1 positive input ) pc5 adc9 (analog input channel 9) amp1+ (analog differential amplifier 1 input channel ) pc4 adc8 (analog input channel 8) amp1- (analog differential amplifier 1 input channel ) pc3 t1 (timer 1 clock input) pscout23 output pc2 t0 (timer 0 clock input) pscout22 output pc1 pscin1 (psc 1 digital input) oc1b (timer 1 output compare b) pc0 pscout10 output (see note 4) int3 66 at90pwm216/316 [datasheet] 7710h?avr?07/2013 ? adc10/acmp1 ? bit 6 adc10, analog to digital converter, input channel 10. acmp1, analog comparator 1 positive i nput. configure the port pin as input wi th the internal pull-up switched off to avoid the digital port function from interferin g with the function of the analog comparator. ? adc9/amp1+ ? bit 5 adc9, analog to digital converter, input channel 9. amp1+, analog differential amplifier 1 positive input channel. ? adc8/amp1- ? bit 4 adc8, analog to digital converter, input channel 8. amp1-, analog differential amplifier 1 negative input channel. ? t1/pscout23 ? bit 3 t1, timer/counter1 counter source. pscout23: output 3 of psc 2. ? t0/pscout22 ? bit 2 t0, timer/counter0 counter source. pscout22: output 2 of psc 2. ? pscin1/oc1b, bit 1 pcsin1, psc 1 digital input. oc1b, output compare match b output: this pin can serve as an external output for the timer/counter1 output compare b. the pin has to be configured as an output (ddc1 set ?one?) to serve this function. this pin is also the output pin for the pwm mode timer function. ? pscout10/int3 ? bit 0 pscout10: output 0 of psc 1. int3, external interrupt so urce 3: this pin can serve as an external interrupt source to the mcu. 67 at90pwm216/316 [datasheet] 7710h?avr?07/2013 table 10-7 and table 10-8 relate the alternate functions of port c to the overriding signals shown in figure 10-5 on page 61 . table 10-7. overriding signals for alternate functions in pc7..pc4 signal name pc7/d2a pc6/adc10/ acmp1 pc5/adc9/ amp1+ pc4/adc8/ amp1- puoe 0 0 0 puov 0 0 0 ddoe daen 0 0 0 ddov 0 0 0 0 pvoe 0 0 0 ? pvov 0 0 0 ? dieoe daen adc10d adc9d adc8d dieov 0 0 0 0 di aio ? adc10 amp1 adc9 amp1+ adc8 amp1- table 10-8. overriding signals for alternate functions in pc3..pc0 signal name pc3/t1/ pscout23 pc2/t0/ pscout22 pc1/pscin1/ oc1b pc0/int3/ pscout10 puoe0000 puov0000 ddoe pscen23 pscen22 0 pscen10 ddov1101 pvoe pscen23 pscen22 oc1ben pscen10 pvov pscout23 pscout22 oc1b pscout10 dieoe in3en dieov in3en di t1 t0 pscin1 int3 aio 68 at90pwm216/316 [datasheet] 7710h?avr?07/2013 10.3.4 alternate functions of port d the port d pins with alternate functions are shown in table 10-9 . the alternate pin configuration is as follows: ? acmp0 ? bit 7 acmp0, analog comparator 0 positive i nput. configure the port pin as input wi th the internal pull-up switched off to avoid the digital port function from interferin g with the function of the analog comparator. ? adc3/acmpm/int0 ? bit 6 adc3, analog to digital converter, input channel 3. acmpm, analog comparators negative input. configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interferin g with the function of the analog comparator. int0, external interrupt so urce 0. this pin can serve as an external interrupt source to the mcu. ? adc2/acmp2 ? bit 5 adc2, analog to digital converter, input channel 2. acmp2, analog comparator 1 positive i nput. configure the port pin as input wi th the internal pull-up switched off to avoid the digital port function from interferin g with the function of the analog comparator. ? adc1/rxd/icp1/sck_a ? bit 4 adc1, analog to digital converter, input channel 1. table 10-9. port d pins alternate functions port pin alternate function pd7 acmp0 (analog comparator 0 positive input ) pd6 adc3 (analog input channel 3 ) acmpm reference for analog comparators int0 pd5 adc2 (analog input channel 2) acmp2 (analog comparator 2 positive input ) pd4 adc1 (analog input channel 1) rxd (dali/uart rx data) icp1 (timer 1 input capture) sck_a (programming & alternate spi clock) pd3 txd (dali/uart tx data) oc0a (timer 0 output compare a) ss (spi slave select) mosi_a (programming & alternate spi master out slave in) pd2 pscin2 (psc 2 digital input) oc1a (timer 1 output compare a) miso_a (programming & alternate master in spi slave out) pd1 pscin0 (psc 0 digital input ) clko (system clock output) pd0 pscout00 output xck (uart transfer clock) ss_a (alternate spi slave select) 69 at90pwm216/316 [datasheet] 7710h?avr?07/2013 rxd, usart receive pin. receive data (data input pi n for the usart). when the usart receiver is enabled this pin is configured as an input regardless of the val ue of ddrd4. when the usart forces this pin to be an input, a logical one in portd4 will turn on the internal pull-up. icp1 ? input capture pin1: this pin can act as an input capture pi n for timer/counter1. sck_a: master clock output, slave clock input pin for spi ch annel. when the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddd4 . when the spi is enabled as a master, the data direction of this pin is controlled by ddd4. w hen the pin is forced to be an input, the pull-up can still be controlled by the portd4 bit. ? txd/oc0a/ss/mosi_a, bit 3 txd, uart transmit pin. data output pin for the usart. when the usart tran smitter is enabled, this pin is con- figured as an output regardless of the value of ddd3. oc0a, output compare match a output: this pin can serve as an external output for the timer/counter0 output compare a. the pin has to be configured as an output (ddd3 set ?one?) to serve this function. the oc0a pin is also the output pin for the pwm mode ss : slave port select input. when the spi is enabled as a slav e, this pin is configured as an input regardless of the setting of ddd3. as a slave, the spi is activated when this pin is driven low. when the spi is enabled as a master, the data direction of this pin is contro lled by ddd3. when the pin is forced to be an input, the pull-up can still be controlled by the portd3 bit. mosi_a: spi master data output, slave data input for spi channel. wh en the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddd3 when the spi is enabled as a master, the data direction of this pin is controlled by ddd3. w hen the pin is forced to be an input, the pull-up can still be controlled by the portd3 bit. ? pscin2/oc1a/miso_a, bit 2 pcsin2, psc 2 digital input. oc1a, output compare match a output: this pin can serve as an external output for the timer/counter1 output compare a. the pin has to be configured as an output (ddd2 set ?one?) to serve this function. the oc1a pin is also the output pin for the pwm mode timer function. miso_a: master data input, slave data output pin for spi channel. when the spi is enabled as a master, this pin is configured as an input regardless of the setting of ddd 2. when the spi is enabled as a slave, the data direction of this pin is controlled by ddd2. w hen the pin is forced to be an input, the pull-up can still be controlled by the portd2 bit. ? pscin0/clko ? bit 1 pcsin0, psc 0 digital input. clko, divided system clock: the divide d system clock can be output on this pin. the divided system clock will be output if the ckout fuse is programmed, rega rdless of the portd1 and ddd1 se ttings. it will also be output dur- ing reset. ? pscout00/xck/ss_a ? bit 0 pscout00: output 0 of psc 0. xck, usart external cl ock. the data direction register (ddd0) cont rols whether the clock is output (ddd0 set) or input (ddd0 cleared). the xck0 pin is active only when the usart operates in synchronous mode. ss _a: slave port select input. when the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddd0. as a slave, the spi is activated when this pin is driven low. when the spi is enabled as a 70 at90pwm216/316 [datasheet] 7710h?avr?07/2013 master, the data direction of this pin is controlled by ddd0. when the pin is forced to be an input, the pull-up can still be controlled by the portd0 bit. table 10-10 and table 10-11 relates the alternate functions of port d to the overriding signals shown in figure 10- 5 on page 61 . table 10-10. overriding signals for alternate functions pd7..pd4 signal name pd7/ acmp0 pd6/adc3/ acmpm/int0 pd5/adc2/ acmp2 pd4/adc1/rxd/ icp1a/sck_a puoe 0 0 0 rxen + spe ? mstr ? spips puov 0 0 0 pd4 ? pud ddoe 0 0 0 rxen + spe ? mstr ? spips ddov 0 0 0 0 pvoe 0 0 0 spe ? mstr ? spips pvov 0 0 0 ? dieoe acmp0d adc3d + in0en adc2d adc1d dieov 0 in0en 0 0 di ? int0 icp1a aio acomp0 adc3 acmpm adc2 acomp2 adc1 table 10-11. overriding signals for alte rnate functions in pd3..pd0 signal name pd3/txd/oc0a/ ss/mosi_a pd2/pscin2/ oc1a/miso_a pd1/pscin0/ clko pd0/pscout00/xck/ss_a puoe txen + spe ? mstr ? spips ? 0 spe ? mstr ? spips puov txen ? spe ? mstr ? spips ? pd3 ? pud ? 0 pd0 ? pud ddoe txen + spe ? mstr ? spips ? 0 pscen00 + spe ? mstr ? spips ddov txen 0 0 pscen00 pvoe txen + oc0en + spe ? mstr ? spips ? 0 pscen00 + umsel pvov txen ? txd + txen ? (oc0en ? oc0 + oc0en ? spips ? mosi) ?0? dieoe 0 0 0 0 dieov 0 0 0 0 di ss mosi_ain ss_a aio 71 at90pwm216/316 [datasheet] 7710h?avr?07/2013 10.3.5 alternate functions of port e the port e pins with alternate functions are shown in table 10-12 . the alternate pin configuration is as follows: ? xtal2/adc0 ? bit 2 xtal2: chip clock oscillator pin 2. used as clock pin for crystal osc illator or low-frequency crystal oscillator. when used as a clock pin, the pin can not be used as an i/o pin. adc0, analog to digital converter, input channel 0. ? xtal1/oc0b ? bit 1 xtal1: chip clock oscillator pin 1. used for all chip cl ock sources except internal calibrated rc oscillator. when used as a clock pin, the pin can not be used as an i/o pin. oc0b, output compare match b output: this pin can serve as an external output for the timer/counter0 output compare b. the pin has to be configured as an output (dde1 set ?one?) to serve this function. this pin is also the output pin for the pwm mode timer function. ? reset /ocd ? bit 0 reset , reset pin: when the rstdisbl fuse is programmed, th is pin functions as a normal i/o pin, and the part will have to rely on power-on reset and brown-out reset as its reset source s. when the rstdisbl fuse is unpro- grammed, the reset circuitry is connected to the pin, and the pin can not be used as an i/o pin. if pe0 is used as a reset pin, dde0, porte0 and pine0 will all read 0. table relates the alternate functions of port e to the overriding signals shown in figure 10-5 on page 61 . table 10-12. port e pins alternate functions port pin alternate function pe2 xtal2: xtal output adc0 (analog input channel 0) pe1 xtal1: xtal input oc0b (timer 0 output compare b) pe0 reset# (reset input) ocd (on chip debug i/o) 72 at90pwm216/316 [datasheet] 7710h?avr?07/2013 overriding signals for alternate functions in pe2..pe0 signal name pe2/adc0/ xtal2 pe1/oc0b pe0/reset / ocd puoe 0 0 0 puov 0 0 0 ddoe 0 0 0 ddov 0 0 0 pvoe 0 oc0ben 0 pvov 0 oc0b 0 dieoe adc0d 0 0 dieov 0 0 0 di aio osc output adc0 osc / clock input 73 at90pwm216/316 [datasheet] 7710h?avr?07/2013 10.4 register description for i/o-ports 10.4.1 port b data register ? portb 10.4.2 port b data di rection register ? ddrb 10.4.3 port b input pins address ? pinb 10.4.4 port c data register ? portc 10.4.5 port c data di rection register ? ddrc 10.4.6 port c input pins address ? pinc 10.4.7 port d data register ? portd 10.4.8 port d data di rection register ? ddrd bit 76543210 portb7 portb6 portb5 portb4 port b3 portb2 portb1 portb0 portb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 ddrb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 pinb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 portc7 portc6 portc5 portc4 port c3 portc2 portc1 portc0 portc read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 ddrc read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 pinc7 pinc6 pinc5 pinc4 pinc3 pinc2 pinc1 pinc0 pinc read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 portd7 portd6 portd5 portd4 port d3 portd2 portd1 portd0 portd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 ddrd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 74 at90pwm216/316 [datasheet] 7710h?avr?07/2013 10.4.9 port d input pins address ? pind 10.4.10 port e data register ? porte 10.4.11 port e data dire ction register ? ddre 10.4.12 port e input pins address ? pine bit 76543210 pind7 pind6 pind5 pind4 pind3 pind2 pind1 pind0 pind read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 ? ? ? ? ? porte2 porte1 porte0 porte read/write rrrrrr/wr/wr/w initial value00000000 bit 76543210 ? ? ? ? ? dde2 dde1 dde0 ddre read/write rrrrrr/wr/wr/w initial value00000000 bit 76543210 ? ? ? ? ? pine2 pine1 pine0 pine read/write rrrrrr/wr/wr/w initial value00000n/an/an/a 75 at90pwm216/316 [datasheet] 7710h?avr?07/2013 11. external interrupts the external interrupts are triggered by the int3:0 pins . observe that, if enabled, th e interrupts will trigger even if the int3:0 pins are configured as outputs. this feature provides a way of generating a software interrupt. the external interr upts can be triggered by a falling or ri sing edge or a low level. this is set up as indicated in the spec- ification for the external interrupt co ntrol registers ? eicra (int3:0). when the external interrupt is enabled and is configured as level triggere d, the interrupt will trigger as long as the pin is held low. note t hat recognition of fall- ing or rising edge interrupts on int3:0 requir es the presence of an i/o clock, described in ?clock systems and their distribution? on page 25 . the i/o clock is halted in all sleep modes except idle mode. note that if a level trigger ed interrupt is used for wake -up from power-down mode, the changed level must be held for some time to wake up the mcu. this makes the mc u less sensitive to noise. the changed level is sampled twice by the watchdog oscillator clock. the period of t he watchdog oscillator is 1 s (nominal) at 5.0v and 25 ? c. the frequency of the watchdog oscillator is voltage dependent as shown in the ?electrical characteristics? on page 283 . the mcu will wake up if the input ha s the required level during this samp ling or if it is held until the end of the start-up time. the start-up time is defined by the sut fuses as described in ?system clock? on page 25 . if the level is sampled twice by the watchdog oscilla tor clock but disappears before the end of the start-up time, the mcu will still wake up, but no interrupt will be gen erated. the required le vel must be held lo ng enough for the mcu to complete the wake up to trigger the level interrupt. 11.0.1 external interrupt control register a ? eicra ? bits 7..0 ? isc31, isc30 ? isc01, isc00: external interrupt 3 - 0 sense control bits the external interrupts 3 - 0 are activated by the exte rnal pins int3:0 if the sreg i-flag and the corresponding interrupt mask in the eimsk is set. the level and edges on the external pins that activate the interrupts are defined in table 11-1 . edges on int3..int0 are registered asynchronous ly.the value on the int3:0 pins are sampled before detecting edges. if edge or toggle interrupt is se lected, pulses that last lon ger than one cl ock period will gen- erate an interrupt. shorter pulses ar e not guaranteed to generate an interrupt. observe that cpu clock frequency can be lower than the xtal frequency if the xtal divider is enabled. if low leve l interrupt is selected, the low level must be held until the completion of the currently executi ng instruction to generate an interrupt. if enabled, a level triggered interrupt will generate an in terrupt request as long as the pin is held low. note: 1. n = 3, 2, 1 or 0. when changing the iscn1/iscn0 bits, the interrupt must be disabled by clearing its interrupt enable bit in the eimsk register. otherwise an interrupt can occur when the bits are changed. bit 76543210 isc31 isc30 isc21 isc20 isc11 isc10 isc01 isc00 eicra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 table 11-1. interrupt sense control (1) iscn1 iscn0 description 0 0 the low level of intn generates an interrupt request. 0 1 any logical change on intn generates an interrupt request 1 0 the falling edge between two samples of intn generates an interrupt request. 1 1 the rising edge between two samples of intn generates an interrupt request. 76 at90pwm216/316 [datasheet] 7710h?avr?07/2013 11.0.2 external interrupt mask register ? eimsk ? bits 3..0 ? int3 ? int0: extern al interrupt request 3 - 0 enable when an int3 ? int0 bit is written to one and the i-bit in the status register (sreg) is set (one), the correspond- ing external pin interrupt is enabled. the interrupt sense control bits in the external interrupt control register ? eicra ? defines whether the external interrupt is activated on rising or falling edge or level sensed. activity on any of these pins will trigger an interrupt re quest even if the pin is enabled as an output. this provides a way of gener- ating a software interrupt. 11.0.3 external interrupt flag register ? eifr ? bits 3..0 ? intf3 - intf0: external interrupt flags 3 - 0 when an edge or logic change on the int3:0 pin triggers an interrupt request, intf3:0 becomes set (one). if the i- bit in sreg and the corresponding interrupt enable bit, int3:0 in eimsk, are set (one), the mcu will jump to the interrupt vector. the flag is cleared when the interrupt ro utine is executed. alternativel y, the flag can be cleared by writing a logical one to it. these fl ags are always cleared when int3:0 are configured as level interrupt. bit 76543210 ----int3int2int1iint0eimsk read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 bit 76543210 ----intf3intf2intf1iintf0eifr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 77 at90pwm216/316 [datasheet] 7710h?avr?07/2013 12. timer/counter0 and ti mer/counter1 prescalers timer/counter1 and timer/counter0 share the same presca ler module, but the timer/counters can have different prescaler settings. the description below applies to both timer/counter1 and timer/counter0. 12.0.1 internal clock source the timer/counter can be clocked directly by the system cl ock (by setting the csn2:0 = 1). this provides the fast- est operation, with a maximum timer/counter clock frequency equal to system clock frequency (f clk_i/o ). alternatively, one of four taps from the prescaler can be used as a clock source. the prescaled clock has a fre- quency of either f clk_i/o /8, f clk_i/o /64, f clk_i/o /256, or f clk_i/o /1024. 12.0.2 prescaler reset the prescaler is free running, i.e., operates independently of the clock select logic of the timer/counter, and it is shared by timer/counter1 and timer/c ounter0. since the prescaler is not af fected by the timer/counter?s clock select, the state of the prescaler will ha ve implications for situations where a prescaled clock is used. one example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 > csn2:0 > 1). the number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to n+1 system clock cycles, where n equals the prescaler divisor (8, 64, 256, or 1024). it is possible to use the prescaler reset for synchronizi ng the timer/counter to program execution. however, care must be taken if the other timer/counter that shares the same prescaler also uses prescaling. a prescaler reset will affect the prescaler period for all timer/counters it is connected to. 12.0.3 external clock source an external clock source applied to the tn/t 0 pin can be used as timer/counter clock (clk t1 /clk t0 ). the tn/t0 pin is sampled once every system clock c ycle by the pin synchronization logic. the synchronized (sampled) signal is then passed through the edge detector. figure 12-1 shows a functional equivalent block diagram of the tn/t0 syn- chronization and edge detector logic. the registers are cloc ked at the positive edge of the internal system clock ( clk i/o ). the latch is transparent in the high period of the internal system clock. the edge detector generates one clk t1 /clk t 0 pulse for each positive (csn2:0 = 7) or negative (csn2:0 = 6) edge it detects. figure 12-1. tn/t0 pin sampling the synchronization and edge detector logic introduces a dela y of 2.5 to 3.5 system clock cycles from an edge has been applied to the tn/t0 pin to the counter is updated. enabling and disabling of the clock input must be done wh en tn/t0 has been stable for at least one system clock cycle, otherwise it is a risk that a fa lse timer/counter clock pulse is generated. each half period of the external clock applied must be longer than one system clock cycle to ensure correct sam- pling. the external clock must be guaranteed to have less than half the system clock frequency (f extclk < f clk_i/o /2) given a 50/50% duty cycle. since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (nyquist sampling theorem). however, due to variation of the system clock frequency and duty cycle caused by oscillator source (crystal, resonator, and capacitors) tolerances, it is rec- ommended that maximum frequency of an external clock source is less than f clk_i/o /2.5. tn_sync (to clock select logic) edge detector synchronization dq dq le dq tn clk i/o 78 at90pwm216/316 [datasheet] 7710h?avr?07/2013 an external clock source can not be prescaled. figure 12-2. prescaler for timer/counter0 and timer/counter1 (1) note: 1. the synchronization logic on the input pins ( tn/t0) is shown in figure 12-1 . 12.0.4 general timer/counte r control register ? gtccr ? bit 7 ? tsm: timer/counter synchronization mode writing the tsm bit to one activates the timer/counter synchronization mode. in this mode, the value that is writ- ten to the psrsync bit is kept, hence keeping the corre sponding prescaler reset signals asserted. this ensures that the corresponding timer/counters are halted and can be configured to the same value without the risk of one of them advancing during configuratio n. when the tsm bit is written to ze ro, the psrsync bit is cleared by hard- ware, and the timer/counters start counting simultaneously. ? bit6 ? icpsel1: timer 1 input capture selection timer 1 capture function has two poss ible inputs icp1a (pd4) and icp1b (p b6). the selection is made thanks to icpsel1 bit as described in table . ? bit 0 ? psrsync: prescaler reset when this bit is one, timer/counter1 and timer/coun ter0 prescaler will be reset. this bit is normally cleared immediately by hardware, except if the tsm bit is set. note that timer/counter1 and timer/counter0 share the same prescaler and a reset of this prescaler will affect both timers. psrsync clear clk t1 clk t0 t1 t0 clk i/o synchronization synchronization bit 7 6 543 2 1 0 tsm icpsel1 ? ? ? ? ? psrsync gtccr read/write r/w r/w r r r r r r/w initial value 0 0 0 0 0 0 0 0 table 12-1. icpsel1 icpsel1 description 0 select icp1a as trigger for timer 1 input capture 1 select icp1b as trigger for timer 1 input capture 79 at90pwm216/316 [datasheet] 7710h?avr?07/2013 13. 8-bit timer/counter0 with pwm timer/counter0 is a general purpose 8-bit timer/counter module, with two independent output compare units, and with pwm support. it allows ac curate program execution timing (event management) and wave generation. the main features are: ? two independent output compare units ? double buffered output compare registers ? clear timer on compare match (auto reload) ? glitch free, phase correct pulse width modulator (pwm) ? variable pwm period ? frequency generator ? three independent interrupt sources (tov0, ocf0a, and ocf0b) 13.1 overview a simplified block diagram of the 8-bit timer/counter is shown in figure 13-1 . for the actual placement of i/o pins, refer to ?pin descriptions? on page 8 . cpu accessible i/o registers, includi ng i/o bits and i/o pins, are shown in bold. the device-specific i/o register and bit locations are listed in the ?8-bit timer/counter register description? on page 89 . the prtim0 bit in ?power reduction register? on page 37 must be written to zero to enable timer/counter0 module. figure 13-1. 8-bit timer/counter block diagram 13.1.1 definitions many register and bit references in this section are written in general form. a lo wer case ?n? replaces the timer/counter number, in this case 0. a lower case ?x? replaces the output compare unit, in this case compare unit a or compare unit b. ho wever, when using the register or bit defin es in a program, the precise form must be used, i.e., tcnt0 for accessing timer/counter0 counter value and so on. timer/counter data b u s = tcntn waveform generation ocna control logic count clear direction tovn (int.req.) ocrnx tccrna clock select tn edge detector ( from prescaler ) clk tn ocna (int.req.) = ocrnx waveform generation ocnb ocnb (int.req.) tccrnb = fixed top v alues = 0 top bottom 80 at90pwm216/316 [datasheet] 7710h?avr?07/2013 the definitions in table 13-1 are also used extensively throughout the document. 13.1.2 registers the timer/counter (tcnt0) and output compare registers (ocr0a and ocr0b) are 8-bit registers. interrupt request (abbreviated to int.req. in the figure) signals are a ll visible in the timer interrup t flag register (tifr0). all interrupts are individually masked with the timer interr upt mask register (timsk0). tifr0 and timsk0 are not shown in the figure. the timer/counter can be clocked internally, via the prescale r, or by an external cloc k source on the t0 pin. the clock select logic block controls which clock source and edge the timer/counter uses to increment (or decrement) its value. the timer/counter is inactive when no clock source is selected. the output from the clock select logic is referred to as the timer clock (clk t0 ). the double buffered output compare registers (ocr0a a nd ocr0b) are compared with the timer/counter value at all times. the result of the compare can be used by the waveform generator to generate a pwm or variable fre- quency output on the output compare pins (oc0a and oc0b). see ?using the output compare unit? on page 105. for details. the compare match event will also set t he compare flag (ocf0a or ocf0b) which can be used to generate an output compare interrupt request. 13.2 timer/counter clock sources the timer/counter can be clocked by an internal or an ex ternal clock source. the clock source is selected by the clock select logic which is controlled by the clock select (cs02:0) bits loca ted in the timer/counter control reg- ister (tccr0b). for de tails on clock sources and prescaler, see ?timer/counter0 and timer/counter1 prescalers? on page 77 . 13.3 counter unit the main part of the 8-bit timer/counter is the programmable bi-directional counter unit. figure 13-2 shows a block diagram of the coun ter and its surroundings. figure 13-2. counter unit block diagram table 13-1. definitions bottom the counter reaches the bottom when it becomes 0x00. max the counter reaches its maximum wh en it becomes 0xff (decimal 255). top the counter reaches the top when it be comes equal to the highest value in the count sequence. the top value can be assigned to be the fixed value 0xff (max) or the value stored in the ocr0a register. the assignment is depen- dent on the mode of operation. data bus tcntn control logic count tovn (int.req.) clock select top tn edge detector ( from prescaler ) clk tn bottom direction clear 81 at90pwm216/316 [datasheet] 7710h?avr?07/2013 signal description (internal signals): count increment or decrement tcnt0 by 1. direction select between increment and decrement. clear clear tcnt0 (set all bits to zero). clk t n timer/counter clock, referred to as clk t0 in the following. top signalize that tcnt0 ha s reached maximum value. bottom signalize that tcnt0 has re ached minimum value (zero). depending of the mode of operation used, the counter is cl eared, incremented, or decr emented at each timer clock (clk t0 ). clk t0 can be generated from an external or internal cl ock source, selected by the clock select bits (cs02:0). when no clock source is se lected (cs02:0 = 0) the timer is stopped. however, the tcnt0 value can be accessed by the cpu, regardless of whether clk t0 is present or not. a cpu write overrides (has priority over) all counter clear or count operations. the counting sequence is determined by the setting of the wgm01 and wgm00 bits located in the timer/counter control register (tccr0a) and the wg m02 bit located in the timer/counter control register b (tccr0b). there are close connections between how t he counter behaves (counts) and how waveforms are generated on the out- put compare outputs oc0a and oc0b. for more deta ils about advanced counting sequences and waveform generation, see ?modes of operation? on page 84 . the timer/counter overflow flag (tov0) is set according to the mode of oper ation selected by the wgm02:0 bits. tov0 can be used for generating a cpu interrupt. 13.4 output compare unit the 8-bit comparator continuously compares tcnt0 wi th the output compare registers (ocr0a and ocr0b). whenever tcnt0 equals ocr0a or ocr0b, the comparator signals a match. a match will set the output com- pare flag (ocf0a or ocf0b) at the next timer clock cycl e. if the corresponding interrupt is enabled, the output compare flag generates an output compare interrupt. the output compare flag is automatically cleared when the interrupt is executed. alternatively, the flag can be cleared by software by wr iting a logical one to its i/o bit loca- tion. the waveform generator uses the match signal to generate an output acco rding to operating mode set by the wgm02:0 bits and compare output mode (com0x1:0) bi ts. the max and bottom signals are used by the wave- form generator for handling the special cases of th e extreme values in some modes of operation ( ?modes of operation? on page 84 ). figure 13-3 shows a block diagram of the output compare unit. 82 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 13-3. output compare unit, block diagram the ocr0x registers are double buffered when using an y of the pulse width modulation (pwm) modes. for the normal and clear timer on compare (ctc) modes of operat ion, the double buffering is disabled. the double buff- ering synchronizes the update of the ocr0x compare regi sters to either top or bottom of the counting sequence. the synchronization prevents the occurrence of odd-length, non-symmetrical pwm pulses, thereby making the output glitch-free. the ocr0x register access may seem complex, but this is not case. when the double buffering is enabled, the cpu has access to the ocr0x buffer regi ster, and if double buffering is di sabled the cpu will access the ocr0x directly. 13.4.1 force output compare in non-pwm waveform generation modes, the match output of the comparator can be forced by writing a one to the force output compare (foc0x) bit. forcing compare match will not set the ocf0x flag or reload/clear the timer, but the oc0x pin will be updated as if a real compare match had occurred (the com0x1:0 bits settings define whether the oc0x pin is set, cleared or toggled). 13.4.2 compare match blocking by tcnt0 write all cpu write operations to the tcnt0 register will block any compare matc h that occur in the next timer clock cycle, even when the timer is stopped. this feature allows ocr0x to be initialized to the same value as tcnt0 without triggering an interrupt when the timer/counter clock is enabled. 13.4.3 using the output compare unit since writing tcnt0 in any mode of operation will bl ock all compare matches for on e timer clock cycle, there are risks involved when changing tcnt0 when using the output compare unit, independently of whether the timer/counter is runnin g or not. if the value written to tcnt0 equals the ocr0x va lue, the compare match will be missed, resulting in incorr ect waveform generation. similarly, do not write the tcnt0 value equal to bottom when the counter is down-counting. the setup of the oc0x should be performed before setting the data direction register for the port pin to output. the easiest way of setting the oc0x value is to use the force output co mpare (foc0x) strobe bits in normal mode. the oc0x registers keep their values even wh en changing between waveform generation modes. ocfn x (int.req.) = (8-bit comparator ) ocrnx ocnx data bus tcntn wgmn1:0 waveform generator top focn comnx1:0 bottom 83 at90pwm216/316 [datasheet] 7710h?avr?07/2013 be aware that the com0x1:0 bits are not double bu ffered together with the compare value. changing the com0x1:0 bits will take effect immediately. 13.5 compare match output unit the compare output mode (com0x1:0) bits have two function s. the waveform generator uses the com0x1:0 bits for defining the output compare (o c0x) state at the next compare match. also, the com0x1:0 bits control the oc0x pin output source. figure 13-4 shows a simplified schematic of the l ogic affected by the com0x1:0 bit set- ting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only the parts of the general i/o port control registers (ddr and port) that are affected by the com0x1:0 bits are shown. when referring to the oc0x state, the reference is for the internal oc0x register, no t the oc0x pin. if a system reset occur, the oc0x register is reset to ?0?. figure 13-4. compare match output unit, schematic the general i/o port function is overridden by the outp ut compare (oc0x) from the waveform generator if either of the com0x1:0 bits are set. however, the oc0x pin direct ion (input or output) is still controlle d by the data direc- tion register (ddr) for the port pin. the data direction register bit for the oc0x pin (ddr_oc0x) must be set as output before the oc0x value is visi ble on the pin. the port override functi on is independent of the waveform gen- eration mode. the design of the output compare pin logic allows initia lization of the oc0x state before the output is enabled. note that some com0x1:0 bit settings are reserved for certain modes of operation. see ?8-bit timer/counter reg- ister description? on page 89. 13.5.1 compare output mode and waveform generation the waveform generator uses the com0x1:0 bits diff erently in normal, ctc, and pwm modes. for all modes, setting the com0x1:0 = 0 tells the waveform generator that no action on the oc0x regist er is to be performed on the next compare match. for compare output actions in the non-pwm modes refer to table 13-2 on page 89 . for fast pwm mode, refer to table 13-3 on page 89 , and for phase correct pwm refer to table 13-4 on page 90 . a change of the com0x1:0 bits state will have effect at the first compare matc h after the bits ar e written. for non- pwm modes, the action can be forced to have im mediate effect by usi ng the foc0x strobe bits. port ddr dq dq ocnx pin ocnx dq waveform generator comnx1 comnx0 0 1 data bus focn clk i/o 84 at90pwm216/316 [datasheet] 7710h?avr?07/2013 13.6 modes of operation the mode of operation, i.e., the behavior of the timer/counter and the output compare pins, is defined by the combination of the waveform generation mode (wgm02:0) and compare output mode (com0x1:0) bits. the compare output mode bits do not affect the counting sequence, while the waveform generation mode bits do. the com0x1:0 bits control whether the pwm output generated should be inverted or not (inverted or non-inverted pwm). for non-pwm modes the com0x1:0 bits control whether the output should be set, cleared, or toggled at a compare match ( see ?compare match output unit? on page 83. ). for detailed timing in formation refer to ?timer/counter timing diagrams? on page 88 . 13.6.1 normal mode the simplest mode of operation is the normal mode (wgm02:0 = 0). in this mode the counting direction is always up (incrementing), and no counter clear is performed. the counter simply overruns when it passes its maximum 8- bit value (top = 0xff) and then restarts from the bott om (0x00). in normal operation the timer/counter overflow flag (tov0) will be set in the same ti mer clock cycle as the tcnt0 become s zero. the tov0 flag in this case behaves like a ninth bit, except that it is only set, not cleared. however, comb ined with the timer overflow interrupt that automatically clears the tov0 flag, the timer reso lution can be increased by software. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the output compare unit can be used to generate interrupt s at some given time. using the output compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the cpu time. 13.6.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgm02:0 = 2), the ocr0a register is used to manipulate the counter resolution. in ctc mode the counter is cleared to zero when the counter value (tcnt 0) matches the ocr0a. the ocr0a defines the top value for the counter, hence also its resolution. this mode allows greater control of the compare match output frequency. it also simplifie s the operation of counting external events. the timing diagram for the ctc mode is shown in figure 13-5 . the counter value (tcnt0 ) increases until a com- pare match occurs between tcnt0 and ocr0 a, and then counter (tcnt0) is cleared. figure 13-5. ctc mode, timing diagram an interrupt can be generated each time the counter valu e reaches the top value by using the ocf0a flag. if the interrupt is enabled, the interrupt handler routine can be used for updating the top value. however, changing top to a value close to bottom when the counter is runni ng with none or a low prescaler value must be done with care since the ctc mode does not have the double buffering feature. if the new value written to ocr0a is lower than the current value of tcnt0, the counter will miss the compare match. the count er will then have to count to its maximum value (0xff) and wrap around starti ng at 0x00 before the compare match can occur. for generating a waveform output in ctc mode, the oc0a output can be set to toggle its logical level on each compare match by setting the compare output mode bits to toggle mode (com0a1:0 = 1). the oc0a value will t cntn o cn ( toggle) ocnx interrupt flag set 1 4 p eriod 2 3 (comnx1:0 = 1) 85 at90pwm216/316 [datasheet] 7710h?avr?07/2013 not be visible on the port pin unless the data direction for t he pin is set to output. the waveform generated will have a maximum frequency of f oc0 = f clk_i/o /2 when ocr0a is set to zero (0x00). the waveform frequency is defined by the following equation: the n variable represents the prescale factor (1, 8, 64, 256, or 1024). as for the normal mode of operation, the tov0 flag is set in the same ti mer clock cycle that the counter counts from max to 0x00. 13.6.3 fast pwm mode the fast pulse width modulation or fast pwm mode (wgm02:0 = 3 or 7) provides a high frequency pwm wave- form generation option. the fast pwm differs from the other pwm option by its single-slope operation. the counter counts from bottom to top then restarts from bottom. top is defined as 0xff when wgm2:0 = 3, and ocr0a when wgm2:0 = 7. in non-inverting compare outp ut mode, the output compare (oc0x) is cleared on the compare match between tcnt0 and ocr0x, and set at bo ttom. in inverting compare output mode, the output is set on compare match and cleared at bottom. due to the single-slope operation, the operating frequency of the fast pwm mode can be twice as high as the phase correct pwm mode that use dual-slope operation. this high frequency makes the fast pwm mode well suited for power regulation, rectification, and dac applications. high frequency allows physically small siz ed external components (coils, capacitors), and therefore reduces total sys- tem cost. in fast pwm mode, the counte r is incremented until the counter value matches the top value. the counter is then cleared at the following timer clock cycle. the ti ming diagram for the fast pwm mode is shown in figure 13-6 . the tcnt0 value is in the timing diagram shown as a histogra m for illustrating the single-s lope operation. the diagram includes non-inverted and inverted pwm outputs. the sma ll horizontal line marks on the tcnt0 slopes represent compare matches between ocr0x and tcnt0. figure 13-6. fast pwm mode, timing diagram the timer/counter overflow flag (tov0) is set each time the counter reaches top. if the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. in fast pwm mode, the compare unit allows generation of pwm waveforms on the oc0x pins. setting the com0x1:0 bits to two will produce a non-inverted pwm and an inverted pwm ou tput can be gener ated by setting the com0x1:0 to three: setting the com0a1:0 bits to one allows the oc0a pin to toggle on compare matches if f ocnx f clk_i/o 2 n 1 ocrnx + ?? ?? ------------------------------------------------- - = t cntn ocrnx update and tovn interrupt flag set 1 p eriod 2 3 o cn o cn (comnx1:0 = 2) (comnx1:0 = 3) ocrnx interrupt flag se t 4 5 6 7 86 at90pwm216/316 [datasheet] 7710h?avr?07/2013 the wgm02 bit is set. this option is not available for the oc0b pin (see table 13-6 on page 90 ). the actual oc0x value will only be visible on the port pin if the data direction for the port pin is set as output. the pwm waveform is generated by setting (or clearing) the oc0x register at the compare match between ocr0x and tcnt0, and clearing (or setting) the oc0x register at the timer clock cycle the counter is cleared (changes from top to bottom). the pwm frequency for the output can be calculated by the following equation: the n variable represents the prescale factor (1, 8, 64, 256, or 1024). the extreme values for the ocr0a regi ster represents special cases when generating a pwm waveform output in the fast pwm mode. if the ocr0a is set equal to bottom, the ou tput will be a narrow spike for each max+1 timer clock cycle. setting the ocr0a equal to max will resu lt in a constantly high or low output (depending on the polarity of the output set by the com0a1:0 bits.) a frequency (with 50% duty cycle) waveform output in fast pwm mode can be achieved by setting oc0x to toggle its logical level on each compare match (com0x1:0 = 1). the waveform generated will have a maximum frequency of f oc0 = f clk_i/o /2 when ocr0a is set to zero. this feature is si milar to the oc0a toggle in ctc mode, except the double buffer feature of the output compare unit is enabled in the fast pwm mode. 13.6.4 phase correct pwm mode the phase correct pwm mode (wgm02:0 = 1 or 5) provides a high resolution phase correct pwm waveform gen- eration option. the phase correct pwm mode is based on a dual-slope operation. th e counter counts repeatedly from bottom to top and then from top to bottom. to p is defined as 0xff when wgm2:0 = 1, and ocr0a when wgm2:0 = 5. in non-inverting compare output mode, the output compare (oc0x) is cleared on the com- pare match between tcnt0 and ocr0x while up-counting, and set on the compare match while down-counting. in inverting output compare mode, the operation is in verted. the dual-slope operation has lower maximum opera- tion frequency than single slope operation. however, due to the symmetric feature of the dual-slope pwm modes, these modes are preferred for motor control applications. in phase correct pwm mode the counter is incremented unt il the counter value matches top. when the counter reaches top, it change s the count direction. the tcnt0 value will be eq ual to top for one ti mer clock cycle. the timing diagram for the phase correct pwm mode is shown on figure 13-7 . the tcnt0 value is in the timing dia- gram shown as a histogram for illu strating the dua l-slope operatio n. the diagram incl udes non-inverted and inverted pwm outputs. the small horizontal line mark s on the tcnt0 slopes represent compare matches between ocr0x and tcnt0. f ocnxpwm f clk_i/o n 256 ? ------------------ = 87 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 13-7. phase correct pwm mode, timing diagram the timer/counter overflow flag (tov0) is set each ti me the counter reaches bottom. the interrupt flag can be used to generate an interrupt each time the counter reaches the bottom value. in phase correct pwm mode, the compare unit allows generation of pwm waveforms on the oc0x pins. setting the com0x1:0 bits to two will produce a non-inverted pwm. an inverted pwm output can be generated by setting the com0x1:0 to three: setting the com0 a0 bits to one allows the oc0a pin to toggle on compare matches if the wgm02 bit is set. this option is not available for the oc0b pin (see table 13-7 on page 91 ). the actual oc0x value will only be visible on the port pin if the data direction for the port pin is set as output. the pwm waveform is generated by clearing (or setting) the oc0x register at the compare match between ocr0x and tcnt0 when the counter increments, and setting (or clearing) the oc0x register at compare match between ocr0x and tcnt0 when the counter decrements. the pwm frequency for t he output when using phase correct pwm can be calcu- lated by the following equation: the n variable represents the prescale factor (1, 8, 64, 256, or 1024). the extreme values for the ocr0a register represent special cases when generating a pwm waveform output in the phase correct pwm mode. if the o cr0a is set equal to bottom, the outp ut will be continuously low and if set equal to max the output will be continuously high for non -inverted pwm mode. for inverted pwm the output will have the opposite logic values. at the very start of period 2 in figure 13-7 ocnx has a transition from high to low even though there is no compare match. the point of this transition is to guarantee symmetry around bottom. there are two cases that give a transition without compare match. ? ocrnx changes its value from max, like in figure 13-7 . when the ocr0a value is max the ocn pin value is the same as the result of a down-counting compare match. to ensure symmetry around bottom the ocnx value at max must correspond to the re sult of an up-counting compare match. ? the timer starts counting from a value higher than th e one in ocrnx, and for that reason misses the compare match and hence the ocnx change that would have happened on the way up. tovn interrupt flag set ocnx interrupt flag set 1 2 3 tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) ocrnx update f ocnxpcpwm f clk_i/o n 510 ? ------------------ = 88 at90pwm216/316 [datasheet] 7710h?avr?07/2013 13.7 timer/counter timing diagrams the timer/counter is a synchronous design and the timer clock (clk t0 ) is therefore shown as a clock enable signal in the following figures. the figures include information on when interrupt flags are set. figure 13-8 contains timing data for basic timer/counter operation. the figure shows the count sequence close to the max value in all modes other than phase correct pwm mode. figure 13-8. timer/counter timing diagram, no prescaling figure 13-9 shows the same timing data, but with the prescaler enabled. figure 13-9. timer/counter timing dia gram, with prescaler (f clk_i/o /8) figure 13-10 shows the setting of ocf0b in all modes and ocf0a in all modes except ctc mode and pwm mode, where ocr0a is top. figure 13-10. timer/counter timing diagram, setting of ocf0x, with prescaler (f clk_i/o /8) figure 13-11 shows the setting of ocf0a and the clearing of tcnt0 in ctc mode and fast pwm mode where ocr0a is top. clk tn (clk i/o /1) tovn clk i/o tcntn max - 1 max bottom bottom + 1 tovn tcntn max - 1 max bottom bottom + 1 clk i/o clk tn (clk i/o /8) ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) 89 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 13-11. timer/counter timing diagram, clear timer on compare match mode, with prescaler (f clk_i/o /8) 13.8 8-bit timer/counter register description 13.8.1 timer/counter control register a ? tccr0a ? bits 7:6 ? com0a1:0: compare match output a mode these bits control the output compare pin (oc0a) behavior. if one or both of the com0a1:0 bits are set, the oc0a output overrides the normal port fu nctionality of the i/o pin it is connected to. however, note that the data direction register (ddr) bit corresponding to the oc0a pin must be set in order to enable the output driver. when oc0a is connected to the pin, the function of the com0a1:0 bits depends on the wgm02:0 bit setting. table 13-2 shows the com0a1:0 bit functionality when the wgm02:0 bits are set to a normal or ctc mode (non- pwm). table 13-3 shows the com0a1:0 bit functionality when the wgm01:0 bits are set to fast pwm mode. note: 1. a special case occurs when ocr0a equals top and com0a1 is set. in this case, the compare match is ignored, but the set or clear is done at top. see ?fast pwm mode? on page 85 for more details. ocfnx ocrnx tcntn (ctc) top top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o /8) bit 7 6 5 4 3 210 com0a1 com0a0 com0b1 com0b0 ? ? wgm01 wgm00 tccr0a read/write r/w r/w r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 table 13-2. compare output mode, non-pwm mode com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 0 1 toggle oc0a on compare match 1 0 clear oc0a on compare match 1 1 set oc0a on compare match table 13-3. compare output mode, fast pwm mode (1) com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 01 wgm02 = 0: normal port oper ation, oc0a disconnected. wgm02 = 1: toggle oc0a on compare match. 1 0 clear oc0a on compare match, set oc0a at top 1 1 set oc0a on compare match, clear oc0a at top 90 at90pwm216/316 [datasheet] 7710h?avr?07/2013 table 13-4 shows the com0a1:0 bit functionality when the wg m02:0 bits are set to phase correct pwm mode. note: 1. a special case occurs when ocr0a equals top and com0a1 is set. in this case, the compare match is ignored, but the set or clear is done at top. see ?phase correct pwm mode? on page 109 for more details. ? bits 5:4 ? com0b1:0: compare match output b mode these bits control the output compare pin (oc0b) behavior. if one or both of the com0b1:0 bits are set, the oc0b output overrides the normal port fu nctionality of the i/o pin it is connected to. however, note that the data direction register (ddr) bit corresponding to the oc0b pin must be set in order to enable the output driver. when oc0b is connected to the pin, the function of the com0b1:0 bits depends on the wgm02:0 bit setting. table 13-5 shows the com0b1:0 bit functionality when the wgm02:0 bits are set to a normal or ctc mode (non- pwm). table 13-6 shows the com0b1:0 bit functionality when the wgm02:0 bits are set to fast pwm mode. note: 1. a special case occurs when ocr0b equals top and com0b1 is set. in this case, the compare match is ignored, but the set or clear is done at top. see ?fast pwm mode? on page 85 for more details. table 13-4. compare output mode, phase correct pwm mode (1) com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 01 wgm02 = 0: normal port oper ation, oc0a disconnected. wgm02 = 1: toggle oc0a on compare match. 10 clear oc0a on compare match when up-counting. set oc0a on compare match when down-counting. 11 set oc0a on compare match when up-counting. clear oc0a on compare match when down-counting. table 13-5. compare output mode, non-pwm mode com0b1 com0b0 description 0 0 normal port operation, oc0b disconnected. 0 1 toggle oc0b on compare match 1 0 clear oc0b on compare match 1 1 set oc0b on compare match table 13-6. compare output mode, fast pwm mode (1) com0b1 com0b0 description 0 0 normal port operation, oc0b disconnected. 01reserved 1 0 clear oc0b on compare match, set oc0b at top 1 1 set oc0b on compare match, clear oc0b at top 91 at90pwm216/316 [datasheet] 7710h?avr?07/2013 table 13-7 shows the com0b1:0 bit functionality when the wg m02:0 bits are set to phase correct pwm mode. note: 1. a special case occurs when ocr0b equals top and com0b1 is set. in this case, the compare match is ignored, but the set or clear is done at top. see ?phase correct pwm mode? on page 86 for more details. ? bits 3, 2 ? res: reserved bits these bits are reserved bits in the at90pwm2 16/316 and will always read as zero. ? bits 1:0 ? wgm01:0: waveform generation mode combined with the wgm02 bit found in the tccr0b regist er, these bits control t he counting sequence of the counter, the source for maximum (top) counter value, and what type of waveform generation to be used, see table 13-8 . modes of operation supported by the timer/counter unit are: normal mode (counter), clear timer on compare match (ctc) mode, and two types of pulse width modulation (pwm) modes (see ?modes of operation? on page 84 ). notes: 1. max = 0xff 2. bottom = 0x00 13.8.2 timer/counter control register b ? tccr0b table 13-7. compare output mode, phase correct pwm mode (1) com0b1 com0b0 description 0 0 normal port operation, oc0b disconnected. 01reserved 10 clear oc0b on compare match when up-counting. set oc0b on compare match when down-counting. 11 set oc0b on compare match when up-counting. clear oc0b on compare match when down-counting. table 13-8. waveform generation mode bit description mode wgm02 wgm01 wgm00 timer/count er mode of operation top update of ocrx at tov flag set on (1)(2) 0 0 0 0 normal 0xff immediate max 1001 pwm, phase correct 0xff top bottom 2 0 1 0 ctc ocra immediate max 3 0 1 1 fast pwm 0xff top max 4100reserved ? ? ? 5101 pwm, phase correct ocra top bottom 6110reserved ? ? ? 7111fast pwmocratoptop bit 7 6 5 4 3 210 foc0a foc0b ? ? wgm02 cs02 cs01 cs00 tccr0b read/write w w r r r r r/w r/w initial value 0 0 0 0 0 0 0 0 92 at90pwm216/316 [datasheet] 7710h?avr?07/2013 ? bit 7 ? foc0a: force output compare a the foc0a bit is only active when the wgm bits specify a non-pwm mode. however, for ensuring co mpatibility with future devices, this bit must be set to zero when tccr0b is written when operating in pwm mode. when writing a logical one to the foc0a bit, an immediate compare match is forced on the waveform generation unit. the oc0a output is changed according to its com0a1:0 bits setting. note that the foc0a bit is implemented as a strobe. therefore it is the value present in the com0a1:0 bits that determines the effect of the forced compare. a foc0a strobe will not generate any interrupt, nor will it clear the time r in ctc mode using ocr0a as top. the foc0a bit is always read as zero. ? bit 6 ? foc0b: force output compare b the foc0b bit is only active when the wgm bits specify a non-pwm mode. however, for ensuring co mpatibility with future devices, this bit must be set to zero when tccr0b is written when operating in pwm mode. when writing a logical one to the foc0b bit, an immediate compare match is forced on the waveform generation unit. the oc0b output is changed according to its com0b1:0 bits setting. note that the foc0b bit is implemented as a strobe. therefore it is the value present in the com0b1:0 bits that determines the effect of the forced compare. a foc0b strobe will not generate any interrupt, nor will it clear the timer in ctc mode using ocr0b as top. the foc0b bit is always read as zero. ? bits 5:4 ? res: reserved bits these bits are reserved bits in the at90pwm2 16/316 and will always read as zero. ? bit 3 ? wgm02: waveform generation mode see the description in the ?timer/counter control register a ? tccr0a? on page 89 . ? bits 2:0 ? cs02:0: clock select the three clock select bits select the clo ck source to be used by the timer/counter. if external pin modes are used for the timer/counter0, transit ions on the t0 pin will clock the counter even if the pin is configured as an output. this featur e allows software cont rol of the counting. table 13-9. clock select bit description cs02 cs01 cs00 description 0 0 0 no clock source (timer/counter stopped) 001clk i/o /(no prescaling) 010clk i/o /8 (from prescaler) 011clk i/o /64 (from prescaler) 100clk i/o /256 (from prescaler) 101clk i/o /1024 (from prescaler) 1 1 0 external clock source on t0 pin. clock on falling edge. 1 1 1 external clock source on t0 pin. clock on rising edge. 93 at90pwm216/316 [datasheet] 7710h?avr?07/2013 13.8.3 timer/counter register ? tcnt0 the timer/counter register gives direct access, both for re ad and write operations, to the timer/counter unit 8-bit counter. writing to the tcnt0 register blocks (removes) the compare match on the follo wing timer clock. modify- ing the counter (tcnt0) while the counter is running, introduces a risk of missing a compare match between tcnt0 and the ocr0x registers. 13.8.4 output compare register a ? ocr0a the output compare register a contains an 8-bit value that is continuously compared with the counter value (tcnt0). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc0a pin. 13.8.5 output compare register b ? ocr0b the output compare register b contains an 8-bit value that is continuously compared with the counter value (tcnt0). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc0b pin. 13.8.6 timer/counter interrupt mask register ? timsk0 ? bits 7..3 ? res: reserved bits these bits are reserved bits in the at90pwm2 16/316 and will always read as zero. ? bit 2 ? ocie0b: timer/counter output compare match b interrupt enable when the ocie0b bit is written to one, and the i-bit in the status register is set, the timer/counter compare match b interrupt is enabled. the corresponding interrupt is executed if a compare matc h in timer/counter occurs, i.e., when the ocf0b bit is set in the time r/counter interrupt flag register ? tifr0. ? bit 1 ? ocie0a: timer/counter0 output compare match a interrupt enable when the ocie0a bit is written to one, and the i-bit in the status register is set, the timer/counter0 compare match a interrupt is enabled. the corresponding interrupt is executed if a compare match in timer/counter0 occurs, i.e., when the ocf0a bit is set in the timer/counter 0 interrupt flag register ? tifr0. bit 76543210 tcnt0[7:0] tcnt0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ocr0a[7:0] ocr0a read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ocr0b[7:0] ocr0b read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543 2 10 ?????ocie0bocie0atoie0timsk0 read/write r r r r r r/w r/w r/w initial value00000 0 00 94 at90pwm216/316 [datasheet] 7710h?avr?07/2013 ? bit 0 ? toie0: timer/counter0 overflow interrupt enable when the toie0 bit is written to one, and the i-bit in the status register is set, the timer/counter0 overflow inter- rupt is enabled. the corresponding interr upt is executed if an overflow in timer/counter0 occurs, i.e., when the tov0 bit is set in the timer/counter 0 interrupt flag register ? tifr0. 13.8.7 timer/counter 0 interrupt flag register ? tifr0 ? bits 7..3 ? res: reserved bits these bits are reserved bits in the at90pwm2 16/316 and will always read as zero. ? bit 2 ? ocf0b: timer/counter 0 output compare b match flag the ocf0b bit is set when a compare match occurs between the timer/count er and the data in ocr0b ? output compare register0 b. ocf0b is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, ocf0b is clear ed by writing a logic one to the flag. when the i-bit in sreg, ocie0b (timer/counter compare b match interrupt enable), and ocf0b are set, th e timer/counter compare match interrupt is executed. ? bit 1 ? ocf0a: timer/counter 0 output compare a match flag the ocf0a bit is set when a compare match occurs betwe en the timer/counter0 and the data in ocr0a ? out- put compare register0. ocf0a is cleared by hardwar e when executing the corr esponding interrupt handling vector. alternatively, ocf0a is cleared by writing a lo gic one to the flag. when the i-bit in sreg, ocie0a (timer/counter0 compare match interrupt enable), and ocf0a are set, the timer/counter0 compare match inter- rupt is executed. ? bit 0 ? tov0: timer/counter0 overflow flag the bit tov0 is set when an overflow occurs in timer/co unter0. tov0 is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, tov0 is cleared by writing a logic one to the flag. when the sreg i-bit, toie0 (timer/counter0 ov erflow interrupt enable), and tov0 are set, the timer/counter0 overflow interrupt is executed. the setting of this flag is dependent of the wgm02:0 bit setting. refer to table 13-8 , ?waveform generation mode bit description? on page 91 . bit 76543210 ?????ocf0bocf0atov0tifr0 read/write rrrrrr/wr/wr/w initial value00000000 95 at90pwm216/316 [datasheet] 7710h?avr?07/2013 14. 16-bit timer/counter1 with pwm the 16-bit timer/counter unit allows accurate program execution timing (event man agement), wave generation, and signal timing measurement. the main features are: ? true 16-bit design (i.e., allows 16-bit pwm) ? two independent output compare units ? double buffered output compare registers ? one input capture unit ? input capture noise canceler ? clear timer on compare match (auto reload) ? glitch-free, phase correct pulse width modulator (pwm) ? variable pwm period ? frequency generator ? external event counter ? four independent interrupt sources (tov1, ocf1a, ocf1b, and icf1) 14.1 overview most register and bit references in this section are written in general form. a lower case ?n? replaces the timer/counter number, and a lower case ?x? replaces the ou tput compare unit channel. however, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt1 for accessing timer/counter1 counter value and so on. a simplified block diagram of the 16-bit timer/counter is shown in figure 14-1 . for the actual placement of i/o pins, refer to ?pin descriptions? on page 5 . cpu accessible i/o registers, in cluding i/o bits and i/o pins, are shown in bold. the device-sp ecific i/o register and bit locations are listed in the ?16-bit timer/counter register description? on page 114 . the prtim1 bit in ?power reduction register? on page 37 must be written to zero to enable timer/counter1 module. 96 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 14-1. 16-bit timer/counter block diagram (1) note: 1. refer to table 2.1 on page 5 for timer/counter1 pin placement and description. 14.1.1 registers the timer/counter (tcntn), output compare registers (ocrnx), and input capture register (icrn) are all 16-bit registers. special procedures must be followed when accessing the 16-bit registers. these procedures are described in the section ?accessing 16-bit registers? on page 97 . the timer/counter control registers (tccrnx) are 8-bit registers and have no cpu access restrictions. interrupt requests (abbreviated to int.req. in the figure) signals are all visible in the timer interrupt flag register (tifrn). all interrupts are individually masked with the timer interrupt mask register (timskn). tifrn and timskn are not shown in the figure. the timer/counter can be clocked internally, via the prescale r, or by an external cloc k source on the tn pin. the clock select logic block controls which clock source and edge the timer/counter uses to increment (or decrement) its value. the timer/counter is inactive when no clock source is selected. the output from the clock select logic is referred to as the timer clock (clk t n ). the double buffered output compare registers (ocrnx) are compared with the timer/counter value at all time. the result of the compare can be used by the waveform generator to generate a pwm or variable frequency out- put on the output compare pin (ocnx). see ?output compare units? on page 103. the compare match event will also set the compare match flag (ocfnx) which can be us ed to generate an output compare interrupt request. the input capture register can capt ure the timer/counter va lue at a given external (edge triggered) event on either the input capture pin (icpn). the input capture unit includes a digital filtering unit (noise canceler) for reducing the chance of capturing noise spikes. clock select timer/counter data b u s ocrna ocrnb icrn = = tcntn waveform generation waveform generation ocna ocnb n oise canceler icpnb = fixed top v alues edge detector control logic = 0 top bottom count clear direction tovn (int.req.) ocna (int.req.) ocnb (int.req.) icfn (int.req.) tccrna tccrnb tn edge detector ( from prescaler ) clk tn icpna icpsel1 0 1 97 at90pwm216/316 [datasheet] 7710h?avr?07/2013 the top value, or maximum timer/counter value, can in some modes of operation be defined by either the ocrna register, the icrn register, or by a set of fixed values. when using ocrna as top value in a pwm mode, the ocrna register can not be used for generating a pwm output. however, the top value will in this case be double buffered allowing the top value to be changed in run time. if a fixed to p value is required, the icrn register can be used as an alternative, freeing the ocrna to be used as pwm output. 14.1.2 definitions the following definitions are used extensively throughout the section: 14.2 accessing 16-bit registers the tcntn, ocrnx, and icrn are 16-b it registers that can be accessed by the avr cpu via the 8-bit data bus. the 16-bit register must be byte accessed using two read or write operations. each 16-b it timer has a single 8-bit register for temporary storing of the high byte of the 16 -bit access. the same temporary register is shared between all 16-bit registers within each 16-bit timer. accessing the lo w byte triggers the 16-bit read or write operation. when the low byte of a 16-bit register is written by the cpu, the high byte stored in the temporary register, and the low byte written are both copied into the 16-b it register in the same cl ock cycle. when the low byte of a 16-bit register is read by the cpu, the high byte of the 16-bit register is copied into the temp orary register in the same clock cycle as the low byte is read. not all 16-bit accesses uses the temporary register for the high byte. reading the ocrnx 16-bit registers does not involve using the temporary register. to do a 16-bit write, the high byte must be written befo re the low byte. for a 16-bit read, the low byte must be read before the high byte. the following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. the same principle can be used directly for accessing the ocrnx and icrn registers. note that when using ?c?, the compiler handles the 16-bit access. bottom: the counter reaches the bottom when it becomes 0x0000. max: the counter reaches its max imum when it becomes 0xffff (decimal 65535). top: the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be assigned to be one of the fixed values: 0x00ff, 0x01ff, or 0x03ff, or to the value stored in the ocrna or icrn register. the assignment is dependent of the mode of operation. 98 at90pwm216/316 [datasheet] 7710h?avr?07/2013 note: 1. the example code assumes that the part specific header file is included. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?c bi?, and ?sbi? instructions must be replaced with instructions that allo w access to extended i/o. typically ?lds? and ?sts? combined with ?sbrs?, ?sbrc?, ?sbr?, and ?cbr?. the assembly code example returns the tcntn value in the r17:r16 register pair. it is important to notice that accessing 16-bit registers ar e atomic operations. if an interrupt occurs between the two instructions accessing the 16-bit register, and the interr upt code updates the temporary register by accessing the same or any other of th e 16-bit timer registers, then the result of the access outsid e the interrupt will be corrupted. therefore, when both the main code and the interrupt code update the temporary register, the main code must dis- able the interrupts during the 16-bit access. assembly code examples (1) ... ; set tcnt n to 0x01ff ldi r17,0x01 ldi r16,0xff out tcnt n h,r17 out tcnt n l,r16 ; read tcnt n into r17:r16 in r16,tcnt n l in r17,tcnt n h ... c code examples (1) unsigned int i; ... /* set tcnt n to 0x01ff */ tcnt n = 0x1ff; /* read tcnt n into i */ i = tcnt n ; ... 99 at90pwm216/316 [datasheet] 7710h?avr?07/2013 the following code examples show how to do an atomic re ad of the tcntn register contents. reading any of the ocrnx or icrn registers can be done by using the same principle. note: 1. the example code assumes that the part specific header file is included. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?c bi?, and ?sbi? instructions must be replaced with instructions that allo w access to extended i/o. typically ?lds? and ?sts? combined with ?sbrs?, ?sbrc?, ?sbr?, and ?cbr?. the assembly code example returns the tcntn value in the r17:r16 register pair. assembly code example (1) tim16_readtcnt n : ; save global interrupt flag in r18,sreg ; disable interrupts cli ; read tcnt n into r17:r16 in r16,tcnt n l in r17,tcnt n h ; restore global interrupt flag out sreg,r18 ret c code example (1) unsigned int tim16_readtcnt n ( void ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* read tcnt n into i */ i = tcnt n ; /* restore global interrupt flag */ sreg = sreg; return i; } 100 at90pwm216/316 [datasheet] 7710h?avr?07/2013 the following code examples show how to do an atomic wr ite of the tcntn register c ontents. writi ng any of the ocrnx or icrn registers can be done by using the same principle. note: 1. the example code assumes that the part specific header file is included. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?c bi?, and ?sbi? instructions must be replaced with instructions that allo w access to extended i/o. typically ?lds? and ?sts? combined with ?sbrs?, ?sbrc?, ?sbr?, and ?cbr?. the assembly code example requires that the r17:r16 regi ster pair contains the value to be written to tcntn. 14.2.1 reusing the temporary high byte register if writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. howeve r, note that the same rule of atom ic operation describe d previously also applies in this case. 14.3 timer/counter clock sources the timer/counter can be clocked by an internal or an ex ternal clock source. the clock source is selected by the clock select logic which is controlled by the clock select (csn2:0) bits located in the timer/counter control regis- ter b (tccrnb). for details on clock sources and prescaler, see ?timer/counter0 and timer/counter1 prescalers? on page 77 . assembly code example (1) tim16_writetcnt n : ; save global interrupt flag in r18,sreg ; disable interrupts cli ; set tcnt n to r17:r16 out tcnt n h,r17 out tcnt n l,r16 ; restore global interrupt flag out sreg,r18 ret c code example (1) void tim16_writetcnt n ( unsigned int i ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* set tcnt n to i */ tcnt n = i; /* restore global interrupt flag */ sreg = sreg; } 101 at90pwm216/316 [datasheet] 7710h?avr?07/2013 14.4 counter unit the main part of the 16-bit timer/counter is th e programmable 16-bit bi-directional counter unit. figure 14-2 shows a block diagram of the coun ter and its surroundings. figure 14-2. counter unit block diagram signal description (internal signals): count increment or decrement tcntn by 1. direction select between increment and decrement. clear clear tcntn (set all bits to zero). clk t n timer/counter clock. top signalize that tcntn ha s reached maximum value. bottom signalize that tcntn has re ached minimum value (zero). the 16-bit counter is mapped into two 8-bit i/o memory locations: counter high (tcntnh) containing the upper eight bits of the counter, and counter low (tcntnl) containing the lower eight bits. the tcntnh register can only be indirectly accessed by the cpu. when the cpu does an access to the tcntnh i/o location, the cpu accesses the high byte temporary register (temp). the temporary register is updated with the tcntnh value when the tcntnl is read, and tcntnh is updated with the temporary register value when tcntnl is written. this allows the cpu to read or write the entire 16-bit counter value within one cl ock cycle via the 8- bit data bus. it is important to notice that there are special cases of writi ng to the tcntn register when the counter is counting that will give unpredictable results. the special cases are descr ibed in the sections wher e they are of importance. depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk t n ). the clk t n can be generated from an external or internal clock source, selected by the clock select bits (csn2:0). when no clock source is se lected (csn2:0 = 0) the timer is stopped. however, the tcntn value can be accessed by the cpu, in dependent of whether clk t n is present or not. a cpu write overrides (has priority over) all counter clear or count operations. the counting sequence is deter mined by the setting of the waveform generation mode bits (wgmn3:0) located in the timer/counter control registers a and b (tccrna and tccrnb). there are close connections between how the counter behaves (counts) and how waveforms are ge nerated on the output compare outputs ocnx. for more details about advanced counting seque nces and waveform generation, see ?16-bit timer/counter1 with pwm? on page 95 . the timer/counter overflow flag (tovn) is set according to the mode of oper ation selected by the wgmn3:0 bits. tovn can be used for generating a cpu interrupt. temp (8-bit) data bus (8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) control logic count clear direction tovn (int.req.) clock select top bottom tn edge detector ( from prescaler ) clk tn 102 at90pwm216/316 [datasheet] 7710h?avr?07/2013 14.5 input capture unit the timer/counter incorporates an input capture unit that can capture external events and give them a time- stamp indicating time of occurrence. the external signal indicating an event, or multiple events, can be applied via the icpn pin or alternatively, via the analog-comparator unit. the time-stamps can then be used to calculate fre- quency, duty-cycle, and other features of the signal applied. alternativ ely the time-stamps can be used for creating a log of the events. the input capture unit is illustrated by the block diagram shown in figure 14-3 . the elements of the block diagram that are not directly a part of the input capture unit are gray shaded. the small ?n? in register and bit names indi- cates the timer/counter number. figure 14-3. input capture unit block diagram when a change of the logic level (an event) occurs on the input capture pin (icpn), alternatively on the analog comparator output (aco), and this change confirms to the setting of the edge det ector, a capture will be triggered. when a capture is triggered, the 16-bit value of the counter (tcntn) is written to the input capture register (icrn). the input capture flag (icfn) is set at the same system clock as the tcntn value is copied into icrn register. if enabled (icien = 1), the input capture flag generates an input capture interrupt. the icfn flag is automatically cleared when the interrupt is executed. al ternatively the icfn flag can be cleared by software by writing a logical one to its i/o bit location. reading the 16-bit value in the input capture register (icrn) is done by first reading the low byte (icrnl) and then the high byte (icrnh). when the low byte is read t he high byte is copied into the high byte temporary register (temp). when the cpu reads th e icrnh i/o location it will access the temp register. the icrn register can only be written when using a waveform generation mode that utilizes the icrn register for defining the counter?s top value. in th ese cases the waveform generation mode (wgmn3:0) bits must be set before the top value can be written to t he icrn register. when writing the ic rn register the high byte must be written to the icrnh i/o location before the low byte is written to icrnl. for more information on how to access the 16-bit registers refer to ?accessing 16-bit registers? on page 97 . 14.5.1 input capture trigger source the trigger sources for the input capture unit arethe input capture pin (icp1a & icp1b). icfn (int.req.) write icrn (16-bit register) icrnh ( 8 -bit) n oise canceler icpnb edge detector temp ( 8 -bit) data bus ( 8 -bit) icrnl ( 8 -bit) tcntn (16-bit counter) tcntnh ( 8 -bit) tcntnl ( 8 -bit) icpsel1 icnc ices icpna 103 at90pwm216/316 [datasheet] 7710h?avr?07/2013 be aware that changing trigger source can trigger a capture. the input capture flag must therefore be cleared after the change. the input capture pin (icpn) is sampled using the same technique as for the tn pin ( figure 12-1 on page 77 ). the edge detector is also identical. however, when the noise canc eler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles. note that the input of the noise canceler and edge detector is always enabled unless the timer/counter is set in a waveform generation mode that uses icrn to define top. an input capture can be trigger ed by software by controlling the port of the icpn pin. 14.5.2 noise canceler the noise canceler improves noise immunity by using a si mple digital filtering scheme. the noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. the noise canceler is enabled by setting the input capture noise canceler (icncn) bit in timer/counter control register b (tccrnb). when enabled the noise canceler introduc es additional four system clock cycles of delay from a change applied to the input, to the update of th e icrn register. the noise canceler uses the system clock and is therefore not affected by the prescaler. 14.5.3 using the input capture unit the main challenge when using the input capture unit is to assign enough processor capacity for handling the incoming events. the time between two events is critical. if the processor has not read the captured value in the icrn register before the next event o ccurs, the icrn will be overwritten with a ne w value. in this case the result of the capture will be incorrect. when using the input capture interrupt, the icrn register should be read as early in the interrupt handler routine as possible. even though the input capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. using the input capture unit in any mode of operation when the top value (resolution) is actively changed during operation, is not recommended. measurement of an external signal?s duty cycle requires that the trigger edge is changed after each capture. changing the edge sensing must be done as early as po ssible after the icrn register has been read. after a change of the edge, the input capture flag (icfn) must be cleared by software (writing a logical one to the i/o bit location). for measuring frequency only, the clearing of th e icfn flag is not required (if an interrupt handler is used). 14.6 output compare units the 16-bit comparator continuously compares tcntn with the output compare register (ocrnx). if tcnt equals ocrnx the comparator signals a match. a match will set the output compare flag (ocfnx) at the next ?timer clock cycle?. if enabled (ocienx = 1), the output compare flag generates an output compare interrupt. the ocfnx flag is automatically cleared when the interrupt is ex ecuted. alternatively the ocfnx flag can be cleared by software by writing a logi cal one to its i/o bit location. the waveform generator uses the match signal to gener- ate an output according to operating mode set by the waveform generation mode (wgmn3:0) bits and compare output mode (comnx1:0) bits. the top and bottom signals ar e used by the waveform generator for handling the special cases of the extreme values in some modes of operation ( see ?16-bit timer/counter1 with pwm? on page 95. ) a special feature of output compare unit a allows it to define the timer/counter top value (i.e., counter resolu- tion). in addition to the counter resolution, the top va lue defines the period time for waveforms generated by the waveform generator. 104 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 14-4 shows a block diagram of the output compare unit. the small ?n? in the register and bit names indi- cates the device number (n = n for timer/counter n), and the ?x? indicates output compare unit (x). the elements of the block diagram that are not directly a part of the output compare unit are gray shaded. figure 14-4. output compare unit, block diagram the ocrnx register is double buffered when using any of the twelve pulse width modulation (pwm) modes. for the normal and clear timer on compare (ctc) modes of operation, the double buffering is di sabled. the double buffering synchronizes the update of the ocrnx compare re gister to either top or bottom of the counting sequence. the synchronization prevents the occurrence of odd-length, non-symmetrical pwm pulses, thereby making the output glitch-free. the ocrnx register access may seem complex, but this is not case. when the double buffering is enabled, the cpu has access to the ocrnx buffer regi ster, and if double buffering is di sabled the cpu will access the ocrnx directly. the content of the ocr1x (b uffer or compare) register is on ly changed by a wr ite operation (the timer/counter does not update this register automatically as the tcnt1 and icr1 register). therefore ocr1x is not read via the high byte temporary register (temp). however, it is a good practice to read the low byte first as when accessing other 16-bit registers. writing the ocrnx registers must be done via the temp register since the compare of all 16 bits is done continuously. the high byte (ocrnxh) has to be written first. when the high byte i/o location is written by the cpu, t he temp register will be updated by the value written. then when the low byte (ocrnxl) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the ocrnx buffer or ocrnx compare register in the same system clock cycle. for more information of how to acce ss the 16-bit registers refer to ?accessing 16-bit registers? on page 97 . 14.6.1 force output compare in non-pwm waveform generation modes, the match output of the comparator can be forced by writing a one to the force output compare (focnx) bit. forcing compare match will not set the ocfnx flag or reload/clear the timer, but the ocnx pin will be updated as if a real com pare match had occurred (the comn1:0 bits settings define whether the ocnx pin is set, cleared or toggled). ocfnx (int.req.) = (16-bit comparator ) ocrnx buffer (16-bit register) ocrnxh buf. (8-bit) ocnx temp (8-bit) data bus (8-bit) ocrnxl buf. (8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) comnx1:0 wgmn 3 :0 ocrnx (16-bit register) ocrnxh (8-bit) ocrnxl (8-bit) waveform generator top bottom 105 at90pwm216/316 [datasheet] 7710h?avr?07/2013 14.6.2 compare match blocking by tcntn write all cpu writes to the tcntn register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. this feature allows ocrnx to be initialized to the same va lue as tcntn without trigger- ing an interrupt when the timer/counter clock is enabled. 14.6.3 using the output compare unit since writing tcntn in any mode of operation will bl ock all compare matches for on e timer clock cycle, there are risks involved when changing tcntn when using any of the output compare channels, independent of whether the timer/counter is running or not. if the value written to tcntn equals the ocrnx value, th e compare match will be missed, resulting in incorrect waveform generation. do not write the tcntn equal to top in pwm modes with variable top values. the compare match for the top will be ignored and the counter will continue to 0xffff. similarly, do not write the tcntn value equal to bottom when the counter is down-counting. the setup of the ocnx should be performed before setting the data direction register for the port pin to output. the easiest way of setting the ocnx value is to use the force output co mpare (focnx) strobe bits in normal mode. the ocnx register keeps its value even wh en changing between waveform generation modes. be aware that the comnx1:0 bits are not double bu ffered together with the compare value. changing the comnx1:0 bits will take effect immediately. 14.7 compare match output unit the compare output mode (comnx1:0) bits have two functions. the waveform ge nerator uses the comnx1:0 bits for defining the output compare (ocnx) state at the next compare match. secondly the comnx1:0 bits control the ocnx pin output source. figure 14-5 shows a simplified schematic of the logic affected by the comnx1:0 bit setting. the i/o registers, i/o bits, and i/o pins in the fi gure are shown in bold. only the parts of the general i/o port control registers (ddr and port) that are affected by the comnx1:0 bits are shown. when referring to the ocnx state, the reference is for the internal ocnx regi ster, not the ocnx pin. if a system reset occur, the ocnx register is reset to ?0?. figure 14-5. compare match output unit, schematic port ddr dq dq ocnx pin ocnx dq waveform generator comnx1 comnx0 0 1 data b u s focnx clk i/o 106 at90pwm216/316 [datasheet] 7710h?avr?07/2013 the general i/o port function is overridden by the outp ut compare (ocnx) from the waveform generator if either of the comnx1:0 bits are set. howe ver, the ocnx pin direction (input or output) is still controlled by the data direc- tion register (ddr) for the port pin. the data direction register bit for the oc nx pin (ddr_ocnx) must be set as output before the ocnx value is visibl e on the pin. the port override function is generally independent of the wave- form generation mode, but there are some exceptions. refer to table 14-1 , table 14-2 and table 14-3 for details. the design of the output compare pin logic allows initia lization of the ocnx state before the output is enabled. note that some comnx1:0 bit settings ar e reserved for certain modes of operation. see ?16-bit timer/counter register description? on page 114. the comnx1:0 bits have no effect on the input capture unit. 14.7.1 compare output mode and waveform generation the waveform generator uses the comnx1:0 bits differently in normal, ctc, and pwm modes. for all modes, setting the comnx1:0 = 0 tells the waveform generator that no action on the ocnx regist er is to be performed on the next compare match. for compare output actions in the non-pwm modes refer to table 14-1 on page 115 . for fast pwm mode refer to table 14-2 on page 115 , and for phase correct and phase and frequency correct pwm refer to table 14-3 on page 115 . a change of the comnx1:0 bits state will have effect at the first compare matc h after the bits ar e written. for non- pwm modes, the action can be forced to have im mediate effect by usi ng the focnx strobe bits. 14.8 modes of operation the mode of operation, i.e., the behavior of the timer/counter and the output compare pins, is defined by the combination of the waveform generation mode (wgmn3:0) and compare output mode (comnx1:0) bits. the compare output mode bits do not affect the counting sequence, while the waveform generation mode bits do. the comnx1:0 bits control whether the pwm output generated should be inverted or not (inverted or non-inverted pwm). for non-pwm modes the comnx1:0 bits control whether the output should be set, cleared or toggle at a compare match ( see ?compare match output unit? on page 105. ) for detailed timing in formation refer to ?timer/counter timing diagrams? on page 113 . 14.8.1 normal mode the simplest mode of operation is the normal mode (wgmn3:0 = 0). in this mode the counting direction is always up (incrementing), and no counter clear is performed. the counter simply ov erruns when it passes its maximum 16-bit value (max = 0xffff) and then restarts from the bottom (0x0000). in normal operation the timer/coun- ter overflow flag (tovn) will be set in the same timer clock cycle as the tcntn becomes zero. th e tovn flag in this case behaves like a 17th bit, except that it is only set, not cleared. ho wever, combined with the timer overflow interrupt that automatically clears the tovn flag, the timer resolution can be increased by software. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the input capture unit is easy to use in normal mode. ho wever, observe that the maximum interval between the external events must not exceed the reso lution of the counter. if the interval between events are too long, the timer overflow interrupt or the prescaler must be used to extend the resolution for the capture unit. the output compare units can be used to generate interrupts at some given time. using the output compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the cpu time. 14.8.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgmn3:0 = 4 or 12), the ocrna or icrn register are used to manipu- late the counter resolution. in ctc mode the counter is cleared to zero when the counter value (tcntn) matches either the ocrna (wgmn3:0 = 4) or the icrn (wgmn3:0 = 12). the ocrna or icrn define the top value for the counter, hence also its resolution. this mode allows grea ter control of the compare match output frequency. it also simplifies the operation of counting external events. 107 at90pwm216/316 [datasheet] 7710h?avr?07/2013 the timing diagram for the ctc mode is shown in figure 14-6 . the counter value (tcntn ) increases until a com- pare match occurs with either ocrna or icrn, and then counter (tcntn) is cleared. figure 14-6. ctc mode, timing diagram an interrupt can be generated at each time the counter value reaches the top value by either using the ocfna or icfn flag according to the register used to define the top value. if the interrupt is enabled, the interrupt handler routine can be used for updating the top value. howeve r, changing the top to a value close to bottom when the counter is running with none or a low prescaler va lue must be done with care since the ctc mode does not have the double buffering feature. if the new value written to ocrna or icrn is lower than the current value of tcntn, the counter will miss the compare match. the co unter will then have to co unt to its maximum value (0xffff) and wrap around starting at 0x0000 before the compare match can occur. in many cases this feature is not desirable. an alternative will then be to use the fast pwm mode using ocrna for defining top (wgmn3:0 = 15) since the ocrna then will be double buffered. for generating a waveform output in ctc mode, the ocna output can be set to toggle its logical level on each compare match by setting the compare output mode bits to toggle mode (comna1:0 = 1). the ocna value will not be visible on the port pin unless the data direction for th e pin is set to output (ddr_ocna = 1). the waveform generated will have a ma ximum frequency of f oc n a = f clk_i/o /2 when ocrna is set to zero (0x0000). the waveform frequency is defined by the following equation: the n variable represents the prescaler factor (1, 8, 64, 256, or 1024). as for the normal mode of operation, the tovn flag is set in the same ti mer clock cycle that the counter counts from max to 0x0000. 14.8.3 fast pwm mode the fast pulse width modulation or fast pwm mode (wgmn3:0 = 5, 6, 7, 14, or 15) provides a high frequency pwm waveform generation option. the fast pwm differs from the other pwm options by its single-slope operation. the counter counts from bottom to top then restarts from bottom. in non-inverting compare output mode, the output compare (ocnx) is set on the compar e match between tcntn and ocrnx, and cleared at top. in inverting compare output mode output is cleared on com pare match and set at top. due to the single-slope oper- ation, the operating frequency of the fast pwm mode can be twice as high as the phase correct and phase and frequency correct pwm modes that use dual-slope operatio n. this high frequency ma kes the fast pwm mode well suited for power regulation, rectification, and dac applications. high fre quency allows physically small sized exter- nal components (coils, capacitors), hence reduces total system cost. tcntn ocna (toggle) ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 4 period 2 3 (comna1:0 = 1) f ocna f clk_i/o 2 n 1 ocrna + ?? ?? -------------------------------------------------- - = 108 at90pwm216/316 [datasheet] 7710h?avr?07/2013 the pwm resolution for fast pwm can be fixed to 8-, 9-, or 10-bit, or defined by either icrn or ocrna. the mini- mum resolution allowed is 2-bit (icrn or ocrna set to 0x0003), and the maximum resolution is 16-bit (icrn or ocrna set to max). the pwm resolu tion in bits can be calculated by using the following equation: in fast pwm mode the counter is incremented until the counter value matches either one of the fixed values 0x00ff, 0x01ff, or 0x03ff (wgmn3:0 = 5, 6, or 7), the value in icrn (wgmn3:0 = 14), or the value in ocrna (wgmn3:0 = 15). the counter is then cleared at the foll owing timer clock cycle. the timing diagram for the fast pwm mode is shown in figure 14-7 . the figure shows fast pwm mode w hen ocrna or icrn is used to define top. the tcntn value is in the timing diagram shown as a histogram for illu strating the single -slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcntn slopes represent compare matches between ocrnx and tcntn. the ocnx interrup t flag will be set when a com- pare match occurs. figure 14-7. fast pwm mode, timing diagram the timer/counter overflow flag (tovn) is set each time the counter reaches top. in addition the ocna or icfn flag is set at the same timer clock cyc le as tovn is set when either ocrna or icrn is used for defining the top value. if one of the interrupts are enabled, the interrupt handler routine can be used for updating the top and com- pare values. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare regi sters. if the top value is lo wer than any of the compare registers, a compare match will never occur between the tcntn and the ocrnx. note that when using fixed top values the unused bits are masked to zero when any of the ocrnx registers are written. the procedure for updating icrn differs from updating ocrna when used for defining the top value. the icrn register is not double buffered. this means that if icrn is changed to a low value when the counter is running with none or a low prescaler value, there is a risk that the new icrn value writ ten is lower than the current value of tcntn. the result will then be that the counter will mi ss the compare match at the top value. the counter will then have to count to the max value (0xffff) and wrap around starting at 0x0000 before the compare match can occur. the ocrna register however, is double buffered. this feature allows the ocrn a i/o location to be written anytime. when the ocrna i/o location is written the value written will be put into the ocrna buffer register. the ocrna compare register will then be updated with the value in the buffer register at the next timer clock cycle the tcntn matches top. the update is done at the same timer clock cycle as the tcntn is cleared and the tovn flag is set. r fpwm top 1 + ?? log 2 ?? log ---------------------------------- - = tcntn ocrnx/top update and tovn interrupt flag set and ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 7 period 2 3 4 5 6 8 ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) 109 at90pwm216/316 [datasheet] 7710h?avr?07/2013 using the icrn register for defining top works well w hen using fixed top values. by using icrn, the ocrna register is free to be used for generating a pwm outp ut on ocna. however, if the base pwm frequency is actively changed (by changing the top value), using the ocrna as top is clearly a better choice due to its double buffer feature. in fast pwm mode, the compare units allow generation of pwm waveforms on the ocnx pins. setting the comnx1:0 bits to two will produce a non-inverted pwm and an inverted pwm ou tput can be gener ated by setting the comnx1:0 to three (see table on page 115 ). the actual ocnx value will only be visible on the port pin if the data direction for the port pin is set as output (ddr_o cnx). the pwm waveform is generated by setting (or clear- ing) the ocnx register at the compare match between ocrnx and tcntn, and clearing (or setting) the ocnx register at the timer clock cycle the counter is cleared (changes from top to bottom). the pwm frequency for the output can be calculated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocrnx register represents s pecial cases when generating a pwm waveform output in the fast pwm mode. if the ocrnx is set equal to bottom (0x0000) the output will be a narrow spike for each top+1 timer clock cycle. setting the ocrnx equal to top will result in a constant high or low output (depending on the polarity of the output set by the comnx1:0 bits.) a frequency (with 50% duty cycle) wavefo rm output in fast pwm mode can be achieved by setting ocna to toggle its logical level on each compare match (comna1:0 = 1). th is applies only if ocr1a is used to define the top value (wgm13:0 = 15). the waveform genera ted will have a maximum frequency of f oc n a = f clk_i/o /2 when ocrna is set to zero (0x0000). this feature is similar to the ocna toggle in ctc mode, except the double buffer feature of the output compare unit is enabled in the fast pwm mode. 14.8.4 phase correct pwm mode the phase correct pulse width modulation or phase correct pwm mode (wgmn3:0 = 1, 2, 3, 10, or 11) provides a high resolution phase correct pwm waveform generation option. the phase correct pwm mode is, like the phase and frequency correct pwm mode, based on a dual-slope operation. the counter counts repeatedly from bot- tom (0x0000) to top and then from top to bottom. in non-inverting compare output mode, the output compare (ocnx) is cleared on the compare match between tcntn and ocrnx while upcounting, and set on the compare match while downcounting. in inverting output compare mode, the operation is inverted. the dual-slope operation has lower maximum operation frequency than single slope operation. however, due to the symmetric feature of the dual-slope pwm modes, these modes are preferred for motor control applications. the pwm resolution for the phase correct pwm mode can be fi xed to 8-, 9-, or 10-bit, or defined by either icrn or ocrna. the minimum resoluti on allowed is 2-bit (icrn or ocrna set to 0x0003), and the maximum resolution is 16-bit (icrn or ocrna set to max). the pwm resolution in bits can be calculated by using the following equation: in phase correct pwm mode the counter is incremented unt il the counter value matches either one of the fixed val- ues 0x00ff, 0x01ff, or 0x03ff (wgmn3:0 = 1, 2, or 3) , the value in icrn (wgmn3:0 = 10), or the value in ocrna (wgmn3:0 = 11). the counter has then reached the top and changes the count direction. the tcntn value will be equal to top for one time r clock cycle. the timing diagram for the phase correct pwm mode is shown on figure 14-8 . the figure shows phase correct pwm mode when ocrna or icrn is used to define top. the tcntn value is in the timing diagram shown as a histogram fo r illustrating the dual-sl ope operation. the diagram includes non-inverted and inverted pwm outputs. the sma ll horizontal line marks on the tcntn slopes represent f ocnxpwm f clk_i/o n 1 top + ?? ? ---------------------------------- - = r pcpwm top 1 + ?? log 2 ?? log ---------------------------------- - = 110 at90pwm216/316 [datasheet] 7710h?avr?07/2013 compare matches between ocrnx and tcntn. the ocnx interrupt flag will be set when a compare match occurs. figure 14-8. phase correct pwm mode, timing diagram the timer/counter overflow flag (tovn) is set each time the counter reaches bottom. when either ocrna or icrn is used for defining the top value, the ocna or icfn flag is set accordingly at the same timer clock cycle as the ocrnx registers are updated with the double buffer val ue (at top). the interrupt flags can be used to gener- ate an interrupt each time the counter reaches the top or bottom value. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare regi sters. if the top value is lo wer than any of the compare registers, a compare match will never occur between the tcntn and the ocrnx. note that when using fixed top values, the unused bits are masked to zero when any of the ocrnx registers are written. as the third period shown in figure 14-8 illustrates, changing the top actively while the timer/counter is r unning in the phase correct mode can result in an unsym- metrical output. the reason for this can be found in the time of update of the ocrnx register. since the ocrnx update occurs at top, the pwm period starts an d ends at top. this implies that the length of the falling slope is determined by the previous top value, while the length of the rising slope is determined by the new top value. when these two values differ the two sl opes of the period will differ in length. the difference in length gives the unsymmetrical result on the output. it is recommended to use the phase and frequency correc t mode instead of the phase correct mode when chang- ing the top value while the timer/counter is running. when using a static top value there are practically no differences between the two modes of operation. in phase correct pwm mode, the compare units allow generation of pwm waveforms on the ocnx pins. setting the comnx1:0 bits to two will produce a non-inverted pwm and an inverted pwm output can be generated by set- ting the comnx1:0 to three (see table on page 115 ). the actual ocnx value will only be visible on the port pin if the data direction for the port pin is set as output (ddr_ocnx). the pw m waveform is generated by setting (or clearing) the ocnx register at t he compare match between ocrnx and tcntn when the counter increments, and clearing (or setting) the ocnx register at compare match between ocrnx and tcntn when the counter decre- ocrnx/top update and ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 2 3 4 tovn interrupt flag set (interrupt on bottom) tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) 111 at90pwm216/316 [datasheet] 7710h?avr?07/2013 ments. the pwm frequency for the output when using phase correct pwm can be calculated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocrnx register represent sp ecial cases when generating a pwm waveform output in the phase correct pwm mode. if the ocrnx is set equal to bottom the output will be co ntinuously low and if set equal to top the output will be continuously high for non-inverted pwm mode. for inverted pwm the output will have the opposite logic values. if ocr1a is used to defin e the top value (wgm13:0 = 11) and com1a1:0 = 1, the oc1a output will toggle with a 50% duty cycle. 14.8.5 phase and frequency correct pwm mode the phase and frequency correct pulse width modulation, or phase and frequency correct pwm mode (wgmn3:0 = 8 or 9) provides a high resolution phase and frequency correct pwm waveform generation option. the phase and frequency correct pwm mode is, like the phase correct pwm mode, based on a dual-slope operation. the counter counts repeatedly from bottom (0x0000) to to p and then from top to bottom. in non-inverting com- pare output mode, the output compare (ocnx) is cleared on the compare match between tcntn and ocrnx while up-counting, and set on the compare match while down-counting. in inverting compare output mode, the operation is inverted. the dual-slope operation gives a lower maximum operation frequency compared to the sin- gle-slope operation. however, due to the symmetric feature of the dual -slope pwm modes, these modes are preferred for motor control applications. the main difference between the phase correct, and the phase and frequency correct pwm mode is the time the ocrnx register is updated by the ocrnx buffer register, (see figure 14-8 and figure 14-9 ). the pwm resolution for the phase and frequency correct pwm mode can be defined by either icrn or ocrna. the minimum resolution allowed is 2-bit (icrn or ocrna set to 0x0003), and the maximum resolution is 16-bit (icrn or ocrna set to max). the pwm resolution in bits can be calculated using the following equation: in phase and frequency correct pwm mode the counter is incremented until the counter value matches either the value in icrn (wgmn3:0 = 8), or the value in ocrna (wgmn3:0 = 9). the counter has then reached the top and changes the count direction. the tcnt n value will be equal to top for one timer clock cycle. the timing diagram for the phase correct and frequency correct pwm mode is shown on figure 14-9 . the figure shows phase and fre- quency correct pwm mode when ocrna or icrn is used to define top. the tcntn value is in the timing diagram shown as a histogram for illu strating the dual-slope operation. the diagram in cludes non-inverted and inverted pwm outputs. the small horizontal line mark s on the tcntn slopes represent compare matches between ocrnx and tcntn. the ocnx interrupt flag will be set wh en a compare match occurs. f ocnxpcpwm f clk_i/o 2 ntop ?? --------------------------- - = r pfcpwm top 1 + ?? log 2 ?? log ---------------------------------- - = 112 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 14-9. phase and frequency correct pwm mode, timing diagram the timer/counter overflow flag (tovn) is set at the same timer clock cycle as the ocrnx registers are updated with the double buffer value (at bottom). when either ocrn a or icrn is used for defining the top value, the ocna or icfn flag set when tcntn has reached top. the interrupt flags can then be used to generate an inter- rupt each time the counter reaches the top or bottom value. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare regi sters. if the top value is lo wer than any of the compare registers, a compare match will never occur between the tcntn and the ocrnx. as figure 14-9 shows the output generated is, in contrast to the phase correct mode, symmetrical in all periods. since the ocrnx registers are updated at bottom, the length of the rising and the falling slopes will always be equal. this gives symmetrical output pulses and is therefore frequency correct. using the icrn register for defining top works well w hen using fixed top values. by using icrn, the ocrna register is free to be used for generating a pwm outp ut on ocna. however, if the base pwm frequency is actively changed by changing the top value, us ing the ocrna as top is clearly a better choice due to its double buffer feature. in phase and frequency correct pwm mode, the compar e units allow generation of pwm waveforms on the ocnx pins. setting the comnx1:0 bits to two will produce a non-inve rted pwm and an inverted pwm output can be gen- erated by setting the comnx1:0 to three (see table on page 115 ). the actual ocnx va lue will only be visible on the port pin if the data direction for the port pin is set as output (ddr_ocnx). the pwm waveform is generated by setting (or clearing) the ocnx register at the compar e match between ocrnx and tcntn when the counter incre- ments, and clearing (or setting) th e ocnx register at compare ma tch between ocrnx and tcntn when the counter decrements. the pwm frequency for the output when using phase and frequency correct pwm can be cal- culated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocrnx register represents s pecial cases when generating a pwm waveform output in the phase correct pwm mode. if the ocrnx is set equal to bottom the output will be co ntinuously low and if set equal to top the output will be set to high for non-inverted pw m mode. for inverted pwm th e output will have the ocrnx/top updateand tovn interrupt flag set (interrupt on bottom) ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 2 3 4 tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) f ocnxpfcpwm f clk_i/o 2 ntop ?? --------------------------- - = 113 at90pwm216/316 [datasheet] 7710h?avr?07/2013 opposite logic values. if ocr1a is used to define th e top value (wgm13:0 = 9) and com1a1:0 = 1, the oc1a output will toggle with a 50% duty cycle. 14.9 timer/counter timing diagrams the timer/counter is a synchronous design and the timer clock (clk tn ) is therefore shown as a clock enable signal in the following figures. the figures include information on when interrupt flags are set, and when the ocrnx reg- ister is updated with the ocrnx buffer value (only for modes utilizing double buffering). figure 14-10 shows a timing diagram for the setting of ocfnx. figure 14-10. timer/counter timing diagram, setting of ocfnx, no prescaling figure 14-11 shows the same timing data, but with the prescaler enabled. figure 14-11. timer/counter timing diagram, setting of ocfnx, with prescaler (f clk_i/o /8) figure 14-12 shows the count sequence close to top in various modes. when using phase and frequency correct pwm mode the ocrnx register is updated at bottom. the timing diagrams will be the same, but top should be replaced by bottom, top-1 by bo ttom+1 and so on. the same renaming applies for modes that set the tovn flag at bottom. clk tn (clk i/o /1) ocfnx clk i/o ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) 114 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 14-12. timer/counter timing diagram, no prescaling figure 14-13 shows the same timing data, but with the prescaler enabled. figure 14-13. timer/counter timing dia gram, with prescaler (f clk_i/o /8) 14.10 16-bit timer/counte r register description 14.10.1 timer/counter1 control register a ? tccr1a ? bit 7:6 ? comna1:0: compare output mode for channel a ? bit 5:4 ? comnb1:0: compare output mode for channel b the comna1:0 and comnb1:0 control the output compar e pins (ocna and ocnb respectively) behavior. if one or both of the comna1:0 bits are writt en to one, the ocna output overrides th e normal port functionality of the i/o pin it is connected to. if one or both of the comnb1:0 bi t are written to one, the ocnb output overrides the normal tovn (fpwm) and icfn (if used as top) ocrnx (update at top) tcntn (ctc and fpwm) tcntn (pc and pfc pwm) top - 1 top top - 1 top - 2 old ocrnx value new ocrnx value top - 1 top bottom bottom + 1 clk tn (clk i/o /1) clk i/o tovn (fpwm) and icf n (if used as top) ocrnx (update at top) tcntn (ctc and fpwm) tcntn (pc and pfc pwm) top - 1 top top - 1 top - 2 old ocrnx value new ocrnx value top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o /8) bit 7 6 5 4 3210 com1a1 com1a0 com1b1 com1b0 ? ? wgm11 wgm10 tccr1a read/write r/w r/w r/w r/w r r r/w r/w initial value0 0 0 0 0000 115 at90pwm216/316 [datasheet] 7710h?avr?07/2013 port functionality of the i/ o pin it is connected to. however, note that the data direction register (ddr) bit corre- sponding to the ocna or ocnb pin must be set in order to enable the output driver. when the ocna or ocnb is connected to the pin, the function of the comnx1:0 bits is dependent of the wgmn3:0 bits setting. table 14-1 shows the comnx1:0 bit functionality when th e wgmn3:0 bits are set to a normal or a ctc mode (non-pwm). table 14-2 shows the comnx1:0 bit functionality when th e wgmn3:0 bits are set to the fast pwm mode. note: 1. a special case occurs when ocrna/ocrnb equals top and comna1/comnb1 is set. in this case the compare match is ignored, but the set or clear is done at top. see ?fast pwm mode? on page 107. for more details. table 14-3 shows the comnx1:0 bit functiona lity when the wgmn3:0 bits are set to the phase correct or the phase and frequency correct, pwm mode. note: 1. a special case occurs when ocrna/ocrnb equals top and comna1/comnb1 is set. see ?phase correct pwm mode? on page 109. for more details. table 14-1. compare output mode, non-pwm comna1/comnb1 comna0/comnb0 description 0 0 normal port operation, ocna/ocnb disconnected. 0 1 toggle ocna/ocnb on compare match. 10 clear ocna/ocnb on compare match (set output to low level). 11 set ocna/ocnb on compare match (set output to high level). table 14-2. compare output mode, fast pwm (1) comna1/comnb1 comna0/comnb0 description 0 0 normal port operation, ocna/ocnb disconnected. 01 wgmn3:0 = 14 or 15: toggle oc1a on compare match, oc1b disconnected (normal port operation). for all other wgm1 settings , normal port operation, oc1a/oc1b disconnected. 10 clear ocna/ocnb on compare match, set ocna/ocnb at top 11 set ocna/ocnb on compare match, clear ocna/ocnb at top table 14-3. compare output mode, phase correct and phase and frequency correct pwm (1) comna1/comnb1 comna0/comnb0 description 0 0 normal port operation, ocna/ocnb disconnected. 01 wgmn3:0 = 8, 9 10 or 11: toggle ocna on compare match, ocnb disconnected (normal port operation). for all other wgm1 settings , normal port operation, oc1a/oc1b disconnected. 10 clear ocna/ocnb on compare match when up- counting. set ocna/ocnb on compare match when down-counting. 11 set ocna/ocnb on compare match when up- counting. clear ocna/ocnb on compare match when down-counting. 116 at90pwm216/316 [datasheet] 7710h?avr?07/2013 ? bit 1:0 ? wgmn1:0: waveform generation mode combined with the wgmn3:2 bits found in the tccrnb register, these bits control the counting sequence of the counter, the source for maximum (top) counter value, and what type of waveform generation to be used, see table 14-4 . modes of operation supported by the timer/counter unit are: normal mode (counter), clear timer on compare match (ctc) mode, and three types of pulse width modulation (pwm) modes. ( see ?16-bit timer/counter1 with pwm? on page 95. ). 117 at90pwm216/316 [datasheet] 7710h?avr?07/2013 note: 1. the ctcn and pwmn1:0 bit definition names are obsolete. use the wgm n2:0 definitions. however, the functionality and location of these bits are compatible with previous versions of the timer. 14.10.2 timer/counter1 control register b ? tccr1b ? bit 7 ? icncn: input capture noise canceler setting this bit (to one) activates the input capture noise canceler. when the noise canceler is activated, the input from the input capture pin (icpn) is filtered. the filter function requires four successive equal valued samples of the icpn pin for ch anging its output. the in put capture is th erefore delayed by four os cillator cycl es when the noise canceler is enabled. ? bit 6 ? icesn: input capture edge select this bit selects which edge on the input capture pin (icpn) that is used to tr igger a capture event. when the icesn bit is written to zero, a fallin g (negative) edge is used as trigger, and wh en the icesn bit is written to one, a rising (positive) edge will trigger the capture. when a capture is triggered according to the icesn setting , the counter value is copied into the input capture reg- ister (icrn). the event will also set the input ca pture flag (icfn), and this can be used to cause an input capture interrupt, if this interrupt is enabled. table 14-4. waveform generation mode bit description (1) mode wgmn3 wgmn2 (ctcn) wgmn1 (pwmn1) wgmn0 (pwmn0) timer/counter mode of operation top update of ocrn x at tovn flag set on 0 0 0 0 0 normal 0xffff immediate max 1 0 0 0 1 pwm, phase correct, 8-bit 0x00ff top bottom 2 0 0 1 0 pwm, phase correct, 9-bit 0x01ff top bottom 3 0 0 1 1 pwm, phase correct, 10-bit 0x03ff top bottom 4 0 1 0 0 ctc ocrna immediate max 5 0 1 0 1 fast pwm, 8-bit 0x00ff top top 6 0 1 1 0 fast pwm, 9-bit 0x01ff top top 7 0 1 1 1 fast pwm, 10-bit 0x03ff top top 81000 pwm, phase and frequency correct icrn bottom bottom 91001 pwm, phase and frequency correct ocrna bottom bottom 10 1 0 1 0 pwm, phase correct icrn top bottom 11 1 0 1 1 pwm, phase correct ocrna top bottom 12 1 1 0 0 ctc icrn immediate max 13 1 1 0 1 (reserved) ? ? ? 14 1 1 1 0 fast pwm icrn top top 151111fast pwm ocrnatoptop bit 7654 3210 icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 tccr1b read/write r/w r/w r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 118 at90pwm216/316 [datasheet] 7710h?avr?07/2013 when the icrn is used as top value (see description of the wgmn3:0 bits located in the tccrna and the tccrnb register), the icpn is disconnected and co nsequently the input capt ure function is disabled. ? bit 5 ? reserved bit this bit is reserved for future use. for ensuring compatibili ty with future devices, this bit must be written to zero when tccrnb is written. ? bit 4:3 ? wgmn3:2: waveform generation mode see tccrna register description. ? bit 2:0 ? csn2:0: clock select the three clock select bits select the clock source to be used by the timer/counter, see figure 14-10 and figure 14-11 . if external pin modes are used for the timer/countern, transit ions on the tn pin will clock the counter even if the pin is configured as an output. this featur e allows software cont rol of the counting. 14.10.3 timer/counter1 control register c ? tccr1c ? bit 7 ? focna: force output compare for channel a ? bit 6 ? focnb: force output compare for channel b the focna/focnb bits are only active when the wgmn3: 0 bits specifies a non-pwm mode. however, for ensur- ing compatibility with future devices, these bits must be set to zero when tccrna is written when operating in a pwm mode. when writing a logical one to the focna/focn b bit, an immediate compare match is forced on the waveform generation unit. the ocna/ocn b output is changed according to its comnx1:0 bits setting. note that the focna/focnb bits are implemented as strobes. therefore it is the value present in the comnx1:0 bits that determine the effect of the forced compare. a focna/focnb strobe will not generate any interrupt nor will it clear the ti mer in clear timer on compare match (ctc) mode using ocrna as top. the focna/focnb bits are always read as zero. table 14-5. clock select bit description csn2 csn1 csn0 description 0 0 0 no clock source (timer/counter stopped). 001clk i/o /1 (no prescaling) 010clk i/o /8 (from prescaler) 011clk i/o /64 (from prescaler) 100clk i/o /256 (from prescaler) 101clk i/o /1024 (from prescaler) 1 1 0 external clock source on tn pin. clock on falling edge. 1 1 1 external clock source on tn pin. clock on rising edge. bit 7654 3210 foc1a foc1b ? ? ? ? ? ? tccr1c read/write r/w r/w r r r r r r initial value 0 0 0 0 0 0 0 0 119 at90pwm216/316 [datasheet] 7710h?avr?07/2013 14.10.4 timer/counter1 ? tcnt1h and tcnt1l the two timer/counter i/o locations (tcntnh and tcntnl, combined tcntn) give direct access, both for read and for write operations, to the timer/counter unit 16-bit counter. to ensure that both the high and low bytes are read and written simultaneously when the cpu accesses these registers, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing 16-bit registers? on page 97. modifying the counter (tcntn) while the counter is running introduces a risk of missing a compare match between tcntn and one of the ocrnx registers. writing to the tcntn register blocks (removes) the comp are match on the following timer clock for all compare units. 14.10.5 output compare regist er 1 a ? ocr1ah and ocr1al 14.10.6 output compare regist er 1 b ? ocr1bh and ocr1bl the output compare registers contain a 16-bit value th at is continuously compared with the counter value (tcntn). a match can be used to generate an output compare interrupt, or to generate a waveform output on the ocnx pin. the output compare registers are 16-bit in size. to ensure that both the high and low bytes are written simultane- ously when the cpu writes to these registers, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing 16-bit registers? on page 97. 14.10.7 input capture register 1 ? icr1h and icr1l the input capture is updated with the counter (tcntn) value each time an event occurs on the icpn pin (or optionally on the analog comparator output for timer/counter1). the input capture can be used for defining the counter top value. the input capture register is 16-bit in size. to ensure that both the high and low bytes are read simultaneously when the cpu accesses these register s, the access is performed using an 8-bit temporary high byte register bit 76543210 tcnt1[15:8] tcnt1h tcnt1[7:0] tcnt1l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ocr1a[15:8] ocr1ah ocr1a[7:0] ocr1al read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ocr1b[15:8] ocr1bh ocr1b[7:0] ocr1bl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 icr1[15:8] icr1h icr1[7:0] icr1l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 120 at90pwm216/316 [datasheet] 7710h?avr?07/2013 (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing 16-bit registers? on page 97. 14.10.8 timer/counter1 interrupt mask register ? timsk1 ? bit 7, 6 ? res: reserved bits these bits are unused bits in the at90 pwm216/316, and will a lways read as zero. ? bit 5 ? icie1: timer/counter1, input capture interrupt enable when this bit is written to one, and the i-flag in the status register is set (int errupts globally enabled), the timer/counter1 input capture interrupt is enabled. the corresponding interrupt vector ( table 9-2 on page 52 ) is executed when the icf1 flag, located in tifr1, is set. ? bit 4, 3 ? res: reserved bits these bits are unused bits in the at90 pwm216/316, and will a lways read as zero. ? bit 2 ? ocie1b: timer/counter1, output compare b match interrupt enable when this bit is written to one, and the i-flag in the status register is set (int errupts globally enabled), the timer/counter1 output compare b match interrupt is enabled. the corresponding interrupt vector ( table 9-2 on page 52 ) is executed when the ocf1b flag, located in tifr1, is set. ? bit 1 ? ocie1a: timer/counter1, output compare a match interrupt enable when this bit is written to one, and the i-flag in the status register is set (int errupts globally enabled), the timer/counter1 output compare a match interrupt is enabled. the corresponding interrupt vector ( table 9-2 on page 52 ) is executed when the ocf1a flag, located in tifr1, is set. ? bit 0 ? toie1: timer/counter1, overflow interrupt enable when this bit is written to one, and the i-flag in the status register is set (int errupts globally enabled), the timer/counter1 overflow interrupt is enabled. the corresponding interrupt vector (see ?reset and interrupt vec- tors placement in at90pwm216/316(1)? on page 52) is ex ecuted when the tov1 flag, located in tifr1, is set. 14.10.9 timer/counter1 interrupt flag register ? tifr1 ? bit 7, 6 ? res: reserved bits these bits are unused bits in the at90 pwm216/316, and will a lways read as zero. ? bit 5 ? icf1: timer/counter1, input capture flag this flag is set when a capture event occurs on the icp1 pin. when the input capture register (icr1) is set by the wgmn3:0 to be used as the top value, the icf1 flag is set when the counter reaches the top value. icf1 is automatically cleared when the input capture inte rrupt vector is executed. alternatively, icf1 can be cleared by writing a logic one to its bit location. ? bit 4, 3 ? res: reserved bits bit 765432 10 ? ? icie1 ? ? ocie1b ocie1a toie1 timsk1 read/write r r r/w r r r/w r/w r/w initial value000000 00 bit 76543210 ??icf1??ocf1bocf1atov1tifr1 read/write r r r/w r r r/w r/w r/w initial value00000000 121 at90pwm216/316 [datasheet] 7710h?avr?07/2013 these bits are unused bits in the at90 pwm216/316, and will a lways read as zero. ? bit 2 ? ocf1b: timer/counter1, output compare b match flag this flag is set in the timer clock cycle after the count er (tcnt1) value matches the output compare register b (ocr1b). note that a forced output compare (foc 1b) strobe will not set the ocf1b flag. ocf1b is automatically cleared when the output compar e match b interrupt vector is executed. alternatively, ocf1b can be cleared by writing a logic one to its bit location. ? bit 1 ? ocf1a: timer/counter1, output compare a match flag this flag is set in the timer clock cycle after the count er (tcnt1) value matches the output compare register a (ocr1a). note that a forced output compare (foc 1a) strobe will not set the ocf1a flag. ocf1a is automatically cleared when the output compar e match a interrupt vector is executed. alternatively, ocf1a can be cleared by writing a logic one to its bit location. ? bit 0 ? tov1: timer/c ounter1, overflow flag the setting of this flag is dependent of the wgmn3:0 bits setting. in normal and ctc modes, the tov1 flag is set when the timer overflows. refer to table 14-4 on page 117 for the tov1 flag behavior when using another wgmn3:0 bit setting. tov1 is automatically cleared when the timer/counter1 overflow interrupt vector is executed. alternatively, tov1 can be cleared by writing a logic one to its bit location. 122 at90pwm216/316 [datasheet] 7710h?avr?07/2013 15. power stage controller ? (psc0, psc1 & psc2) the power stage controller is a high performance waveform controller. 15.1 features ? pwm waveform generation fu nction (2 complementary programmable outputs) ? dead time control ? standard mode up to 12 bit resolution ? frequency resolution enhancement mode (12 + 4 bits) ? frequency up to 64 mhz ? conditional waveform on ex ternal events (zero crossing, current sensing ...) ? all on chip psc synchronization ? adc synchronization ? overload protec tion function ? abnormality protection function, emergency input to force all outputs to low level ? center aligned and edge aligned modes synchronization ? fast emergency stop by hardware 15.2 overview many register and bit references in this section are written in general form. ? a lower case ?n? replaces the psc nu mber, in this case 0, 1 or 2. however, when using the register or bit defines in a program, the precise form must be used , i.e., psoc1 for accessing psc 1 synchro and output configuration register and so on. ? a lower case ?x? replaces the psc part, in this case a or b. however, when using the register or bit defines in a program, the precise form must be used, i.e., pfrcna for accessing psc n fault/retrigger n a control register and so on. the purpose of a power stage controller (psc) is to c ontrol power modules on a boar d. it has two outputs on psc0 and psc1 and four outputs on psc2. these outputs can be used in various ways: ? ?two outputs? to drive a half bridge (lighting, dc motor ...) ? ?one output? to drive single power transi stor (dc/dc converter, pfc, dc motor ...) ? ?four outputs? in the case of psc2 to drive a full bridge (lighting, dc motor ...) each psc has two inputs the purpose of which is to provide means to act directly on the generated waveforms: ? current sensing regulation ? zero crossing retriggering ? demagnetization retriggering ? fault input the psc can be chained and synchronized to provide a configuration to driv e three half bridges. thanks to this feature it is possible to generate a three phase waveform s for applications such as asynchronous or bldc motor drive. 123 at90pwm216/316 [datasheet] 7710h?avr?07/2013 15.3 psc description figure 15-1. power stage controller 0 or 1 block diagram note: n = 0, 1 the principle of the psc is based on th e use of a counter (psc counter). this counter is able to count up and count down from and to values stored in registers according to the selected running mode. the psc is seen as two symmetrical entities. one par t named part a which generates the output pscoutn0 and the second one named part b which generates the pscoutn1 output. each part a or b has its own psc inpu t module to manage selected input. databus ocrnrb ocrnsb ocrnra = = = psc counter waveform generator b psc input module b psc input module a pscoutn1 pctln pfrcna psocn ( from analog comparator n ouput ) ocrnsa = pcnfn pfrcnb pom2(psc2 only) picrn waveform generator a pscoutn0 pscinn part b part a piselnb piselna pscn input b pscn input a 124 at90pwm216/316 [datasheet] 7710h?avr?07/2013 15.3.1 psc2 distinctive feature figure 15-2. psc2 versus psc1&psc0 block diagram note: n = 2 psc2 has two supplementary outputs pscout22 and psco ut23. thanks to a first selector pscout22 can duplicate pscout20 or pscout21. thanks to a sec ond selector pscout23 can duplicate pscout20 or pscout21. the output matrix is a kind of 2*2 look up table which gi ves the possibility to program the output values according to a psc sequence ( see ?output matrix? on page 150. ) 15.3.2 output polarity the polarity ?active high? or ?active low? of the psc outputs is programmable. all the timing diag rams in the follow- ing examples are given in the ?active high? polarity. databus ocrnrb ocrnsb ocrnra = = = psc counter waveform generator b psc input module b psc input module a pscoutn1 pctln pfrcna psocn ( from analog comparator n ouput ) ocrnsa = pcnfn pfrcnb pom2(psc2 only) picrn waveform generator a pscoutn0 pscinn part a part b pscoutn2 pscoutn3 piselnb piselna pscn input b pscn input a pos23 pos22 output matrix 125 at90pwm216/316 [datasheet] 7710h?avr?07/2013 15.4 signal description figure 15-3. psc external block view note: 1. available only for psc2 2. n = 0, 1 or 2 15.4.1 input description table 15-1. internal inputs ocrnrb[11:0] ocrnra[11:0] ocrnsa[11:0] ocrnrb[15:12] ocrnsb[11:0] picrn[11:0] irq pscn synin pscinn analog comparator n output pscoutn0 pscoutn2 synout clk 4 12 12 12 12 clk pscoutn1 pscoutn3 12 pscnasy stopout stopin i/o pll (1) (1) (flank width modulation) name description type width ocrnrb[11:0] compare value which reset signal on part b (pscoutn1) register 12 bits ocrnsb[11:0] compare value which set signal on part b (pscoutn1) register 12 bits ocrnra[11:0] compare value which reset signal on part a (pscoutn0) register 12 bits ocrnsa[11:0] compare value which set signal on part a (pscoutn0) register 12 bits ocrnrb[15:12] frequency resolution enhancement value (flank width modulation) register 4 bits clk i/o clock input from i/o clock signal 126 at90pwm216/316 [datasheet] 7710h?avr?07/2013 note: 1. see figure 15-38 on page 151 table 15-2. block inputs 15.4.2 output description table 15-3. block outputs table 15-4. internal outputs note: 1. see figure 15-38 on page 151 2. see ?analog synchronization? on page 150. clk pll clock input from pll signal synin synchronization in (from adjacent psc) (1) signal stopin stop input (for synchronized mode) signal name description type width pscinn input 0 used for retrigger or fault functions signal from a c input 1 used for retrigger or fault functions signal name description type width name description type width pscoutn0 psc n output 0 (f rom part a of psc) signal pscoutn1 psc n output 1 (f rom part b of psc) signal pscoutn2 (psc2 only) psc n output 2 (from part a or part b of psc) signal pscoutn3( psc2 only) psc n output 3 (from part a or part b of psc) signal name description type width synout synchronization output (1) signal picrn [11:0] psc n input capture register counter value at retriggering event register 12 bits irqpscn psc interrupt request: three sources, overflow, fault, and input capture signal pscnasy adc synchronization (+ amplifier synchro. ) (2) signal stopout stop output (for synchronized mode) 127 at90pwm216/316 [datasheet] 7710h?avr?07/2013 15.5 functional description 15.5.1 waveform cycles the waveform generated by psc can be described as a sequence of two waveforms. the first waveform is relative to pscoutn0 output and part a of psc. the part of this waveform is sub-cycle a in the following figure. the second waveform is relative to pscoutn1 output and part b of psc. the part of this waveform is sub-cycle b in the following figure. the complete waveform is ended with the end of sub-cycle b. it means at the end of waveform b. figure 15-4. cycle presentation in 1, 2 & 4 ramp mode figure 15-5. cycle presentation in centered mode ramps illustrate the output of the psc counter included in the waveform generators. centered mode is like a one ramp mode which count down up and down. notice that the update of a new set of values is done r egardless of ramp mode at the top of the last ramp. 15.5.2 running mode description waveforms and length of output signals are determined by ti me parameters (dt0, ot0, dt1, ot1) and by the running mode. four modes are possible: 4 ramp mode 2 ramp mode 1 ramp mode sub-cycle a sub-cycle b psc cycle update ramp a0 ramp a1 ramp b0 ramp b1 ramp a ramp b psc cycle update centered mode 128 at90pwm216/316 [datasheet] 7710h?avr?07/2013 ? four ramp mode ? two ramp mode ? one ramp mode ? center aligned mode 15.5.2.1 four ramp mode in four ramp mode, each time in a cycle has its own definition figure 15-6. pscn0 & pscn1 basic waveforms in four ramp mode the input clock of psc is given by clkpsc. pscoutn0 and pscoutn1 signals are defined by on-time 0, dead-time 0, on-time 1 and dead-time 1 values with : on-time 0 = ocrnrah/l * 1/fclkpsc on-time 1 = ocrnrbh/l * 1/fclkpsc dead-time 0 = (ocrnsah/l + 2) * 1/fclkpsc dead-time 1 = (ocrnsbh/l + 2) * 1/fclkpsc note: minimal value for dead-time 0 and dead-time 1 = 2 * 1/fclkpsc 15.5.2.2 two ramp mode in two ramp mode, the whole cycle is divided in two moments one moment for pscn0 description with ot0 which gives the time of the whole moment one moment for pscn1 description with ot1 which gives the time of the whole moment on-time 0 on-time 1 pscoutn0 pscoutn1 dead-time 1 dead-time 0 psc cycle ocrnrb ocrnsb ocrnra ocrnsa psc counter 00 129 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 15-7. pscn0 & pscn1 basic waveforms in two ramp mode pscoutn0 and pscoutn1 signals are defined by on-time 0, dead-time 0, on-time 1 and dead-time 1 values with: on-time 0 = (ocrnrah/l - ocrnsah/l) * 1/fclkpsc on-time 1 = (ocrnrbh/l - ocrnsbh/l) * 1/fclkpsc dead-time 0 = (ocrnsah/l + 1) * 1/fclkpsc dead-time 1 = (ocrnsbh/l + 1) * 1/fclkpsc note: minimal value for dead-time 0 and dead-time 1 = 1/fclkpsc 15.5.2.3 one ramp mode in one ramp mode, pscoutn0 and pscoutn1 outputs can overlap each other. on-time 0 on-time 1 pscoutn0 pscoutn1 dead-time 1 dead-time 0 psc cycle ocrnrb ocrnsb ocrnra ocrnsa psc counter 00 130 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 15-8. pscn0 & pscn1 basic wavefo rms in one ramp mode on-time 0 = (ocrnrah/l - ocrnsah/l) * 1/fclkpsc on-time 1 = (ocrnrbh/l - ocrnsbh/l) * 1/fclkpsc dead-time 0 = (ocrnsah/l + 1) * 1/fclkpsc dead-time 1 = (ocrnsbh/l - ocrnrah/l) * 1/fclkpsc note: minimal value for dead-time 0 = 1/fclkpsc 15.5.2.4 center aligned mode in center aligned mode, the center of pscn0 and pscn1 signals are centered. on-time 0 on-time 1 pscoutn0 pscoutn1 dead-time 1 dead-time 0 psc cycle ocrnrb ocrnsb ocrnra ocrnsa psc counter 0 131 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 15-9. pscn0 & pscn1 basic waveforms in center aligned mode on-time 0 = 2 * ocrnsah/l * 1/fclkpsc on-time 1 = 2 * (ocrnrbh/l - ocrnsbh/l + 1) * 1/fclkpsc dead-time = (ocrnsbh/l - ocrnsah/l) * 1/fclkpsc psc cycle = 2 * (ocrnrbh/l + 1) * 1/fclkpsc note: minimal value for psc cycle = 2 * 1/fclkpsc ocrnrah/l is not used to co ntrol psc output waveform timing. neverthe less, it can be useful to adjust adc syn- chronization ( see ?analog synchronization? on page 150. ). figure 15-10. run and stop mechanism in centered mode note: see ?psc 0 control register ? pctl0? on page 157. (or pctl1 or pctl2) on-ti me 1 on-ti me 0 pscoutn 0 pscoutn 1 psc cy cl e dead-time on-ti me 1 dead-time psc co u n t er ocrn rb ocrnsa ocrnsb 0 p scout n0 p sc c ounter o crnr b o crnsa o crnsb 0 r un pscout n1 132 at90pwm216/316 [datasheet] 7710h?avr?07/2013 15.5.3 fifty percent waveform configuration when pscoutn0 and pscoutn1 have the same characteristi cs, it?s possible to configure the psc in a fifty per- cent mode. when the psc is in this configuration, it duplicates the ocrnsbh/l and ocrnrbh/l registers in ocrnsah/l and ocrnrah/l registers. so it is no t necessary to program ocrnsah/l and ocrnrah/l registers. 15.6 update of values to avoid unasynchronous and in coherent values in a cycle, if an update of one of severa l values is necessary, all values are updated at the same time at the end of the cycle by the psc. the new set of values is calculated by software and the update is initiated by software. figure 15-11. update at the end of complete psc cycle. the software can stop the cycle before the end to update the values and restart a new psc cycle. 15.6.1 value update synchronization new timing values or psc output configuration can be written during the psc cycle. thanks to lock and autolock configuration bits, the new whole set of val ues can be taken into account after the end of the psc cycle. when autolock configuration is select ed, the update of th e psc internal registers will be done at the end of the psc cycle if the output compare register rb has been th e last written. the autolock configuration bit is taken into account at the end of the first psc cycle. when lock configuration bit is set, ther e is no update. the update of the psc internal registers will be done at the end of the psc cycle if the lock bit is released to zero. the registers which update is synchronized thanks to lock and autolock are psocn, pom2, ocrnsah/l, ocrnrah/l, ocrnsbh/l and ocrnrbh/l. see these register?s description starting on page 155 . when set, autolock configuration bit prevails over lock configuration bit. see ?psc 0 configuration register ? pcnf0? on page 155. 15.7 enhanced resolution lamp ballast applications need an enh anced resolution down to 50hz. the method to improve the normal resolu- tion is based on flank width modulation (also called fractional divider). cy cles are grouped into frames of 16 cycles. cycles are modulated by a sequence given by the fractional divider number. the resulting output frequency is the average of the frequencies in the frame. the fractional divider (d) is given by ocrnrb[15:12]. software psc regulation loop calculation writting in psc registers cycle with set i cycle with set i cycle with set i cycle with set i cycle with set j end of cycle request for an update 133 at90pwm216/316 [datasheet] 7710h?avr?07/2013 the psc output period is directly equal to the pscoutn0 on time + d ead time (ot0+dt0) and pscoutn1 on time + deadtime (ot1+dt1) values. these values are 12 bits numbers. the frequency adjustment can only be done in steps like the dedicated counters. the step width is defined as the frequency difference between two neighboring psc frequencies: with k is the number of clk psc period in a psc cycle and is given by the following formula: with f op is the output operating frequency. example, in normal mode, with maximum operating frequency 160 khz and f pll = 64mhz, k equals 400. the result- ing resolution is delta f equals 64mhz / 400 / 401 = 400 hz. in enhanced mode, the output frequency is the avera ge of the frame formed by t he 16 consecutive cycles. f b1 and f b2 are two neighboring base frequencies. then the frequency resolution is divided by 16. in the example above, the resolution equals 25 hz. 15.7.1 frequency distribution the frequency modulation is don e by switching two frequencies in a 16 consecutive cycle frame. these two fre- quencies are f b1 and f b2 where f b1 is the nearest base frequency above the wanted frequency and f b2 is the nearest base frequency below the wanted frequency. the number of f b1 in the frame is (d-16) and the number of f b2 is d. the f b1 and f b2 frequencies are evenly dist ributed in the frame according to a pr edefined pattern. this pattern can be as given in the following table or by any other im plementation which give an equ ivalent evenly distribution. ? ff 1 f 2 ? f pll k ---------- f pll k 1 + ----------- - ? f psc 1 kk 1 + ?? ------------------- - ? == = n f psc f op ---------- = f average 16 d ? 16 --------------- f b 1 ? d 16 ------ f b 2 ? + = f average 16 d ? 16 --------------- f pll n ---------- ? d 16 ------ f pll n 1 + ------------ ? + = 134 at90pwm216/316 [datasheet] 7710h?avr?07/2013 table 15-5. distribution of f b2 in the modulated frame while ?x? in the table, f b2 prime to f b1 in cycle corresponding cycle. so for each row, a number of fb2 take place of fb1. figure 15-12. resulting frequency versus d. 15.7.2 modes of operation 15.7.2.1 normal mode the simplest mode of operation is the normal mode. see figure 15-6 . the active time of pscoutn0 is given by the ot0 value. the active time of pscoutn1 is given by the ot1 value. both of them are 12 bit values. thanks to dt0 & dt1 to adjust the dead time between pscoutn0 and pscoutn1 active signals. distribution of fb2 in the modulated frame pwm - cycle fractional divider (d) 0123456789101112131415 0 1x 2x x 3xxx 4xxxx 5xxxxx 6xxx xxx 7 xxxxxxx 8 xxxxxxxx 9 xxxxxxxxx 10 xxx x x xxx x x 11 xxx xxx xxx x x 12 xxx xxx xxx xxx 13 xxxxxxx xxx xxx 14 xxxxxxx xxxxxxx 15 xxxxxxxxxxxxxxx f b1 f b2 d: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 f op 135 at90pwm216/316 [datasheet] 7710h?avr?07/2013 the waveform frequency is defined by the following equation: 15.7.2.2 enhanced mode the enhanced mode uses the previously describe d method to generate a high resolution frequency. figure 15-13. enhanced mode, timing diagram the supplementary step in counting to generate f b2 is added on the pscn0 signal while needed in the frame according to the fractional divider. see table 15-5, ?distribution of fb2 in the modulated frame,? on page 134 . the waveform frequency is defined by the following equations: d is the fractional divider factor. 15.8 psc inputs each part a or b of psc has its own system to take into account one psc input. according to psc n input a/b control register (see description 15.25.14 page 159 ), pscnin0/1 input can act has a retrigger or fault input. this system a or b is also configured by this psc n input a/b contro l register (pfrcna/b). f pscn 1 pscncycle ----------------------------- - = f clk_pscn ot 0 ot 1 dt 0 dt 1 +++ ?? ---------------------------------------------------------------------- = pscoutn0 t1 period pscoutn1 ot0 ot1 dt1 dt0 t2 ot0 ot1+1 dt1 dt0 dt0 f 1 pscn 1 t 1 ----- - f clk_pscn ot 0 ot 1 dt 0 dt 1 +++ ?? ---------------------------------------------------------------------- == f 2 pscn 1 t 2 ----- - f clk_pscn ot 0 ot 1 dt 0 dt 11 ++++ ?? -------------------------------------------------------------------------------- == f average 16 d ? ?? 16 -------------------- f 1 pscn ? d 16 ------ f 2 pscn ? + = 136 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 15-14. psc input module 15.8.1 psc retrigger behaviour vs. psc running modes in centered mode, retrigger inputs have no effect. in two ramp or four ramp mode, retrigger inputs a or b cause the end of the corresponding cycle a or b and the beginning of the following cycle b or a. in one ramp mode, retrigger inputs a or b reset the current psc counting to zero. 15.8.2 retrigger pscoutn0 on external event pscoutn0 output can be reset before end of on-time 0 on the change on pscn input a. pscn input a can be configured to do not act or to act on level or edge modes. t he polarity of pscn input a is configurable thanks to a sense control block. pscn input a can be the output of the analog comparator or the pscinn input. as the period of the cycle decreases, the inst antaneous frequency of the two outputs increases. analog comparator n output pscinn digital filter piselna (piselnb) pfltena (pfltenb) paocna (paocnb) input processing (retriggering ...) psc core (counter, waveform generator, ...) output control 1 0 0 1 pscoutn0 (pscoutn1) (pscout22) (pscout23) clk psc clk psc clk psc pelevna / (pelevnb) prfmna3:0 (prfmnb3:0) pcaena (pcaenb) 2 4 137 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 15-15. pscoutn0 retriggered by pscn input a (edge retriggering) note: this example is given in ?input mode 8? in ?2 or 4 ramp mode? see figure 15-31. for details. figure 15-16. pscoutn0 retriggered by pscn input a (level acting) note: this example is given in ?input mode 1? in ?2 or 4 ramp mode? see figure 15-20. for details. 15.8.3 retrigger pscoutn1 on external event pscoutn1 ouput can be resetted before end of on-time 1 on the change on pscn input b. the polarity of pscn input b is configurable thanks to a sense control block. psc n input b can be configured to do not act or to act on level or edge modes. pscn input b can be the output of the analog comparator or the pscinn input. as the period of the cycle decreases, the inst antaneous frequency of the two outputs increases. on-time 0 on-time 1 pscoutn0 pscoutn1 dead-time 1 dead-time 0 pscn input a (falling edge) pscn input a (rising edge) on-time 0 on-time 1 pscoutn0 pscoutn1 dead-time 1 dead-time 0 pscn input a (high level) pscn input a (low level) 138 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 15-17. pscoutn1 retriggered by pscn input b (edge retriggering) note: this example is given in ?input mode 8? in ?2 or 4 ramp mode? see figure 15-31. for details. figure 15-18. pscoutn1 retriggered by pscn input b (level acting) note: this example is given in ?input mode 1? in ?2 or 4 ramp mode? see figure 15-20. for details. 15.8.3.1 burst generation note: on level mode, it?s possible to use psc to generate burst by using input mode 3 or mode 4 ( see figure 15- 24. and figure 15-25. for details.) on-time 0 on-time 1 pscoutn0 pscoutn1 dead-time 1 dead-time 0 pscn input b dead-time 0 (falling edge) pscn input b (rising edge) on-time 0 on-time 1 pscoutn0 pscoutn1 dead-time 1 dead-time 0 pscn input b dead-time 0 (high level) pscn input b (low level) 139 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 15-19. burst generation 15.8.4 psc input configuration the psc input configuration is done by prog ramming bits in configuration registers. 15.8.4.1 filter enable if the ?filter enable? bit is set, a digital filter of 4 cycles is inserted before evaluation of the signal. the disable of thi s function is mainly needed for prescaled psc clock source s, where the noise cancellation gives too high latency. important: if the digital filter is active, the level sensitivity is true also with a disturbed psc clock to deactivate the outputs (emergency protection of external component). likewise when used as fault input, pscn input a or input b have to go through psc to act on pscoutn0/ 1/2/3 output. this way needs that clk psc is running. so thanks to psc asynchronous output control bit (paocna/b), pscnin0/1 input can des activate directly the psc output. notice that in this case, input is still taken into a ccount as usually by input module system as soon as clk psc is running. psc input filterring 15.8.4.2 signal polarity one can select the active edge (edge modes) or the ac tive level (level modes) see pelevnx bit description in section ?psc n input a control regi ster ? pfrcna?, page 15915.25.14. if pelevnx bit set, the significant edge of pscn input a or b is rising (edge mo des) or the active level is high (level modes) and vice versa for unset/f alling/low off pscoutn0 pscoutn1 pscn input a (high level) pscn input a (low level) burst digital filter 4 x clk psc input module x ouput stage pscoutnx pin pscn input a or b clk psc psc 140 at90pwm216/316 [datasheet] 7710h?avr?07/2013 - in 2- or 4-ramp mode, pscn input a is taken into account only during dead-time0 and on-time0 period (respec- tively dead-time1 and on -time1 for pscn input b). - in 1-ramp-mode psc input a or psc input b act on the whole ramp. 15.8.4.3 input mode operation thanks to 4 configuration bits (prfm3:0), it is possibl e to define all the modes of the pscr input. these modes are listed in table 15-6 . notice: all following examples are given with rising edge or high level active inputs. table 15-6. psc input mode operation prfm3:0 description 0 0000b pscn input has no action on psc output 1 0001b see ?psc input mode 1: stop signal, jump to opposite dead-time and wait? on page 141. 2 0010b see ?psc input mode 2: stop signal, execut e opposite dead-time and wait? on page 142. 3 0011b see ?psc input mode 3: stop signal, execute opposite while fault active? on page 143. 4 0100b see ?psc input mode 4: de activate outputs without changing timing.? on page 144. 5 0101b see ?psc input mode 5: stop signal and insert dead-time? on page 144. 60110b see ?psc input mode 6: stop signal, jump to opposite dead-time and wait.? on page 145. 7 0111b see ?psc input mode 7: halt psc and wait for software action? on page 145. 8 1000b see ?psc input mode 8: edge retrigger psc? on page 146. 9 1001b see ?psc input mode 9: fixed frequency edge retrigger psc? on page 147. 10 1010b reserved: do not use 11 1011b 12 1100b 13 1101b 14 1110b see ?psc input mode 14: fixed frequency edge retrigger psc and disactivate output? on page 148. 15 1111b reserved: do not use 141 at90pwm216/316 [datasheet] 7710h?avr?07/2013 15.9 psc input mode 1: st op signal, jump to oppo site dead-time and wait figure 15-20. pscn behaviour versus pscn input a in fault mode 1 psc input a is taken into account during dt0 and ot0 only. it has no effect during dt1 and ot1. when psc input a event occurs, psc releases pscoutn0, waits for psc input a inactive state and then jumps and executes dt1 plus ot1. figure 15-21. pscn behaviour versus pscn input b in fault mode 1 psc input b is take into account during dt1 and ot1 only. it has no effect during dt0 and ot0. when psc input b event occurs, psc releases pscoutn1, waits for psc input b inactive state and then jumps and executes dt0 plus ot0. pscoutn0 pscoutn1 psc input a psc input b dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 pscoutn0 pscoutn1 psc input a psc input b dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 142 at90pwm216/316 [datasheet] 7710h?avr?07/2013 15.10 psc input mode 2: stop signal, execute opposite dead-time and wait figure 15-22. pscn behaviour versus pscn input a in fault mode 2 psc input a is take into account during dt0 and ot0 only. it has no effect during dt1 and ot1. when pscn input a event occurs, ps c releases pscoutn0, jumps and exec utes dt1 plus ot1 and then waits for psc input a inactive state. even if psc input a is released during dt1 or ot1, dt1 plus ot1 sub-cycle is always completely executed. figure 15-23. pscn behaviour versus pscn input b in fault mode 2 psc input b is take into account during dt1 and ot1 only. it has no effect during dt0 and ot0. when psc input b event occu rs, psc releases pscoutn1, jumps and ex ecutes dt0 plus ot0 and then waits for psc input b inactive state. even if psc input b is released during dt0 or ot0, dt0 plus ot0 sub-cycle is always completely executed. pscoutn0 pscoutn1 psc input a psc input b dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 pscoutn0 pscoutn1 psc input a psc input b dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 143 at90pwm216/316 [datasheet] 7710h?avr?07/2013 15.11 psc input mode 3: stop signal, execute oppo site while fault active figure 15-24. pscn behaviour versus pscn input a in mode 3 psc input a is taken into account during dt0 and ot0 only. it has no effect during dt1 and ot1. when psc input a event occurs, psc releases pscoutn0, jumps and executes dt1 plus ot1 plus dt0 while psc input a is in active state. even if psc input a is released during dt1 or ot1, dt1 plus ot1 sub-cycle is always completely executed. figure 15-25. pscn behaviour versus pscn input b in mode 3 psc input b is taken into account during dt1 and ot1 only. it has no effect during dt0 and ot0. when psc input b event occurs, psc releases pscnout1, jumps and executes dt0 plus ot0 plus dt1 while psc input b is in active state. even if psc input b is released during dt0 or ot0, dt0 plus ot0 sub-cycle is always completely executed. pscoutn0 pscoutn1 psc input a psc input b dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt1 ot1 dt1 ot1 pscoutn0 pscoutn1 psc input a psc input b dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt0 ot0 144 at90pwm216/316 [datasheet] 7710h?avr?07/2013 15.12 psc input mode 4: deactivate outputs without changing timing. figure 15-26. psc behaviour versus pscn input a or input b in mode 4 figure 15-27. psc behaviour versus pscn input a or input b in fault mode 4 pscn input a or pscn input b act indifferently on on-time0/dead-time0 or on on-time1/dead-time1. 15.13 psc input mode 5: stop signal and insert dead-time figure 15-28. psc behaviour versus pscn input a in fault mode 5 used in fault mode 5, pscn input a or pscn input b act indifferently on on-time0/dead-time0 or on on- time1/dead-time1. pscoutn0 pscoutn1 pscn input a or pscn input b dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 pscn input a or pscn input b pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt1 dt1 dt0 dt0 pscn input a or pscn input b dt0 dt1 145 at90pwm216/316 [datasheet] 7710h?avr?07/2013 15.14 psc input mode 6: stop signal, jump to o pposite dead-time and wait. figure 15-29. psc behaviour versus pscn input a in fault mode 6 used in fault mode 6, pscn input a or pscn input b act indifferently on on-time0/dead-time0 or on on- time1/dead-time1. 15.15 psc input mode 7: halt psc and wait for software action figure 15-30. psc behaviour versus pscn input a in fault mode 7 note: 1. software action is the setting of the prunn bit in pctln register. used in fault mode 7, pscn input a or pscn input b act indifferently on on-time0/dead-time0 or on on- time1/dead-time1. pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 pscn input a or pscn input b pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt0 ot0 dt1 ot1 software action (1) pscn input a or pscn input b 146 at90pwm216/316 [datasheet] 7710h?avr?07/2013 15.16 psc input mode 8: edge retrigger psc figure 15-31. psc behaviour versus pscn input a in mode 8 the output frequency is modulated by the occurenc e of significative edge of retriggering input. figure 15-32. psc behaviour versus pscn input b in mode 8 the output frequency is modulated by the occurrence of significative edge of retriggering input. the retrigger event is taken into account only if it occurs during the corresponding on-time. note: in one ramp mode, the retrigger event on input a re sets the whole ramp. so the psc doesn?t jump to the opposite dead-time. pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt0 ot0 dt1 ot1 dt1 ot1 pscn input a pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt0 ot0 dt1 ot1 dt1 ot1 pscn input b pscn input b or 147 at90pwm216/316 [datasheet] 7710h?avr?07/2013 15.17 psc input mode 9: fixed frequency edge retrigger psc figure 15-33. psc behaviour versus pscn input a in mode 9 the output frequency is not modified by the occurence of significative edge of retriggering input. only the output is disactivated when signif icative edge on retriggering input occurs. note: in this mode the output of the psc becomes active during the next ramp even if the retrigger/fault input is actve. only the significative edge of re trigger/fault input is taken into account. figure 15-34. psc behaviour versus pscn input b in mode 9 the retrigger event is taken into account only if it occurs during the corresponding on-time. pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt0 ot0 dt1 ot1 dt1 ot1 pscn input a pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt0 ot0 dt1 ot1 dt1 ot1 pscn input b 148 at90pwm216/316 [datasheet] 7710h?avr?07/2013 15.18 psc input mode 14: fixed frequency edge retrig ger psc and disactivate output figure 15-35. psc behaviour versus pscn input a in mode 14 the output frequency is not modified by the occurence of significative edge of retriggering input. figure 15-36. psc behaviour versus pscn input b in mode 14 the output is disactivated while retriggering input is active. the output of the psc is set to an inactive state and th e corresponding ramp is not aborted. the output stays in an inactive state while the retrigger /fault input is actve. the psc runs at constant frequency. 15.18.1 available input mode according to running mode some input modes are not consistent with some running modes. so the table below gives the input modes which are valid according to running modes.. pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt0 ot0 dt1 ot1 dt1 ot1 dt0 ot0 dt1 ot1 pscn input a pscoutn0 pscoutn1 dt0 ot 0 dt1 ot 1 dt0 ot0 dt0 ot0 dt1 ot1 dt1 ot1 dt0 ot0 dt1 ot1 pscn input b table 15-7. available input modes according to running modes input mode number : 1 ramp mode 2 ramp mode 4 ramp mode centered mode 1 valid valid valid do not use 2 do not use valid valid do not use 3 do not use valid valid do not use 4 valid valid valid valid 149 at90pwm216/316 [datasheet] 7710h?avr?07/2013 15.18.2 event capture the psc can capture the value of time (psc counter) when a retrigger event or fault event occurs on psc inputs. this value can be read by sofware in picrnh/l register. 15.18.3 using the input capture unit there are 2 ways to trigger a capture of the psc counter in the picrn register. ? hardware input capture triggered by a signal on psc inputs. ? software input capture triggered by the pcstn bit the main challenge when using the input capture unit is to assign enough processor capacity for handling the incoming events. the time between two events is critical. if the processor has not read the captured value in the picrn register before the next event occu rs, the picrn will be overwritten with a new value. in this case the result of the capture will be incorrect. when using the input capture interrupt, the picrn register sh ould be read as early in the interrupt handler routine as possible. even though the input capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. 5 do not use valid valid do not use 6 do not use valid valid do not use 7 valid valid valid valid 8 valid valid valid do not use 9 valid valid valid do not use 10 do not use 11 12 13 14 valid valid valid do not use 15 do not use table 15-7. available input modes according to running modes input mode number : 1 ramp mode 2 ramp mode 4 ramp mode centered mode 150 at90pwm216/316 [datasheet] 7710h?avr?07/2013 15.19 psc2 outputs 15.19.1 output matrix psc2 has an output matrix which allow in 4 ramp mo de to program a value of pscout20 and pscout21 binary value for each ramp. pscout2m takes the value given in table 15-8. during a ll corresponding ramp. thanks to the output matrix it is possible to generate all kind of pscout20/pscout21 combination. when output matrix is used, the psc n output polarity popn has no action on the outputs. 15.19.2 pscout22 & pscout23 selectors psc 2 has two supplementary ou tputs pscout22 and pscout23. according to pos22 and pos23 bits in psoc2 r egister, pscout22 and pscout23 duplicate pscout20 and pscou21. if pos22 bit in psoc2 register is clear, pscout22 duplicates pscout20. if pos22 bit in psoc2 register is set, pscout22 dup licates pscout21. if pos23 bit in psoc2 register is clear, pscout23 duplicates pscout21. if pos23 bit in psoc2 register is set, pscout23 dup licates pscout20. figure 15-37. pscout22 and pscout23 outptuts 15.20 analog synchronization psc generates a signal to synchronize the sample and hold; synchronisation is mandatory for measurements. this signal can be selected between all fa lling or rising edge of pscn0 or pscn1 outputs. table 15-8. output matrix versus ramp number ramp 0ramp 1ramp 2ramp 3 pscout20 pomv2a0 pomv2a1 pomv2a2 pomv2a3 pscout21 pomv2b0 pomv2b1 pomv2b2 pomv2b3 pscout20 pscout21 waveform generator a waveform generator b pscout22 pscout23 pos22 pos23 0 1 1 0 output matrix 151 at90pwm216/316 [datasheet] 7710h?avr?07/2013 in center aligned mode, ocrnrah/l is not used, so it can be used to specified the synchronization of the adc. it this case, it?s minimum value is 1. 15.21 interrupt handling as each psc can be dedicated for one function, ea ch psc has its own interrupt system (vector ...) list of interrupt sources: ? counter reload (end of on time 1) ? psc input event (active edge or at th e beginning of level configured event) ? psc mutual synchronization error 15.22 psc synchronization 2 or 3 psc can be synchronized together. in this case, two waveform alignments are possible: ? the waveforms are center aligned in the center aligned mode if master and slaves are all with the same psc period (which is the natural use). ? the waveforms are edge aligned in the 1, 2 or 4 ramp mode figure 15-38. psc run synchronization if the pscn has its parunn bit set, then it can start at the same time as pscn-1. prunn and parunn bits are located in pctln register. see ?psc 0 control register ? pctl0? on page 157. see ?psc 1 control register ? pctl1? on page 158. see ?psc 2 control register ? pctl2? on page 159. note : do not set the parunn bits on the three psc at the same time. parun0 prun0 run psc0 psc0 parun1 prun1 run psc1 psc1 parun2 prun2 run psc2 psc2 sy0out sy0in sy1in sy2in sy1out sy2out 152 at90pwm216/316 [datasheet] 7710h?avr?07/2013 thanks to this feature, we can for example configure two psc in slave mode (parunn = 1 / prunn = 0) and one psc in master mode (parunm = 0 / prunm = 0). this psc master can start a ll psc at the same moment (prunm = 1). 15.22.1 fault events in autorun mode to complete this master/slave mechanism, fault event (input mode 7) is propagated from pscn-1 to pscn and from pscn to pscn-1. a psc which propagate a run signal to the following psc stops this psc when the run signal is deactivate. according to the architecture of the psc synchroni zation which build a ?daisy-chain on the psc run signal? beetwen the three psc, only the faul t event (mode 7) which is able to ?stop? the psc through the prun bits is transmited along this daisy-chain. a psc which receive its run signal from the previous psc transmits its fault signal (if enabled) to this previous psc. so a slave psc propagates its fault even ts when they are configured and enabled. 15.23 psc clock sources psc must be able to generate high frequency with enhanced resolution. each psc has two clock inputs: ? clk pll from the pll ?clk i/o figure 15-39. clock selection pclkseln bit in psc n configuration register (p cnfn) is used to select the clock source. ppren1/0 bits in psc n control re gister (pctln) are used to select the divide factor of the clock. table 15-9. output clock versus selection and prescaler pclkseln ppren1 ppren0 clkpscn output 000clk i/o 0 0 1 clk i/o / 4 0 1 0 clk i/o / 32 0 1 1 clk i/o / 256 100clk pll clk clk pscn clk pll i/o ck ck/4 ck/32 ck/256 prescaler ck ppren1/0 00 01 10 11 pclkseln 1 0 153 at90pwm216/316 [datasheet] 7710h?avr?07/2013 15.24 interrupts this section describes the specif ics of the interrupt handling as performed in at90pwm216/316. 15.24.1 list of interrupt vector each psc provides 2 interrupt vectors ? pscn ec (end of cycle ): when enabled and when a match with ocrnrb occurs ? pscn capt (capture event) : when enabled and one of the two following events occurs : retrigger, capture of the psc counter or synchro error. see pscn interrupt mask register page 162 and pscn interrupt flag register page 163 . 15.24.2 psc interrupt vectors in at90pwm216/316 15.25 psc register definition registers are explained for psc0. they are identical for psc1. for psc2 only different registers are described. 15.25.1 psc 0 synchro and output configuration ? psoc0 15.25.2 psc 1 synchro and output configuration ? psoc1 1 0 1 clk pll / 4 1 1 0 clk pll / 32 1 1 1 clk pll / 256 table 15-9. output clock versus selection and prescaler pclkseln ppren1 ppren0 clkpscn output table 15-10. psc interrupt vectors vector no. program address source interrupt definition -- -- 2 0x0001 psc2 capt psc2 capture event or synchronization error 3 0x0002 psc2 ec psc2 end cycle 4 0x0003 psc1 capt psc1 capture event or synchronization error 5 0x0004 psc1 ec psc1 end cycle 6 0x0005 psc0 capt psc0 capture event or synchronization error 7 0x0006 psc0 ec psc0 end cycle -- -- bit 76543210 - - psync01 psync00 - poen0b - poen0a psoc0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 - - psync11 psync10 - poen1b - poen1a psoc1 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 154 at90pwm216/316 [datasheet] 7710h?avr?07/2013 15.25.3 psc 2 synchro and output configuration ? psoc2 ? bit 7 ? pos23 : pscout 23 selection (psc2 only) when this bit is clear, pscout23 outputs the waveform generated by waveform generator b. when this bit is set, pscout23 outputs the waveform generated by waveform generator a. ? bit 6 ? pos22: pscout22 selection (psc2 only) when this bit is clear, pscout22 outputs the waveform generated by waveform generator a. when this bit is set, pscout22 outputs the waveform generated by waveform generator b. ? bit 5:4 ? psyncn1:0: synchronization out for adc selection select the polarity and signal source for generating a signal which will be sent to the adc fo r synchronization. ? bit 3 ? poen2d : pscout23 output enable (psc2 only) when this bit is clear, second i/o pin af fected to pscout23 acts as a standard port. when this bit is set, i/o pin related to pscout23 is connected to psc2 waveform generator a or b output (according to pos23 setting) and is set and clear according to psc2 operation. ? bit 2 ? poennb: psc n ou t part b output enable when this bit is clear, i/o pin affected to pscoutn1 acts as a standard port. when this bit is set, i/o pin affected to pscoutn1 is connected to the psc waveform generator b output and is set and clear according to the psc operation. ? bit 1 ? poen2c : pscout22 output enable (psc2 only) when this bit is clear, second i/o pin af fected to pscout22 acts as a standard port. bit 76543210 pos23 pos22 psync21 psync20 poen2d poen2b poen2c poen2a psoc2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 15-11. synchronization source descriptio n in one/two/four ramp modes psyncn1 psyncn0 description 0 0 send signal on leading edge of pscoutn0 (match with ocrnsa) 01 send signal on trailing edge of pscoutn0 (match with ocrnra or fault/retrigger on part a) 1 0 send signal on leading edge of pscoutn1 (match with ocrnsb) 11 send signal on trailing edge of pscoutn1 (match with ocrnrb or fault/retrigger on part b) table 15-12. synchronization source description in centered mode psyncn1 psyncn0 description 00 send signal on match with ocrnra ( during counting down of psc). the min value of ocrnra must be 1. 01 send signal on match with ocrnra (during counting up of psc). the min value of ocrnra must be 1. 1 0 no synchronization signal 1 1 no synchronization signal 155 at90pwm216/316 [datasheet] 7710h?avr?07/2013 when this bit is set, i/o pin rela ting to pscout22 is connected to psc2 waveform generator a or b output (according to pos22 setting) and is set and clear according to psc2 operation. ? bit 0 ? poenna: psc n ou t part a output enable when this bit is clear, i/o pin affected to pscoutn0 acts as a standard port. when this bit is set, i/o pin affected to pscoutn0 is connected to the psc waveform generator a output and is set and clear according to the psc operation. 15.25.4 output compare sa regi ster ? ocrnsah and ocrnsal 15.25.5 output compare ra regi ster ? ocrnrah and ocrnral 15.25.6 output compare sb regi ster ? ocrnsbh and ocrnsbl 15.25.7 output compare rb regi ster ? ocrnrbh and ocrnrbl note : n = 0 to 2 according to psc number. the output compare registers ra, rb, sa and sb contain a 12-bit value that is continuously compared with the psc counter value. a match can be used to generate an output compare interrupt, or to generate a waveform out- put on the associated pin. the output compare registers rb contains also a 4-bi t value that is used for the flank width modulation. the output compare registers are 16bit and 12-bit in size. to ensure that both the high and low bytes are written simultaneously when the cpu writes to these registers, the access is perfor med using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. 15.25.8 psc 0 configurat ion register ? pcnf0 bit 76543210 ???? ocrnsa[11:8] ocrnsah ocrnsa[7:0] ocrnsal read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 bit 76543210 ???? ocrnra[11:8] ocrnrah ocrnra[7:0] ocrnral read/write wwwwwwww initial value 00000000 bit 76543210 ???? ocrnsb[11:8] ocrnsbh ocrnsb[7:0] ocrnsbl read/write wwwwwwww initial value 00000000 bit 76543210 ocrnrb[15:12] ocrnrb[11:8] ocrnrbh ocrnrb[7:0] ocrnrbl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 bit 76543210 pfifty0 palock0 plock0 pmode01 pmode00 pop0 pclksel0 - pcnf0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 156 at90pwm216/316 [datasheet] 7710h?avr?07/2013 15.25.9 psc 1 configurat ion register ? pcnf1 15.25.10 psc 2 configurat ion register ? pcnf2 the psc n configuration register is used to configure the running mode of the psc. ? bit 7 - pfiftyn: psc n fifty writing this bit to one, set the psc in a fifty percent mode where only ocrnrbh/l and ocrnsbh/l are used. they are duplicated in ocrnrah/l and ocrnsah/l during the update of ocrnrbh/l. th is feature is useful to perform fifty percent waveforms. ? bit 6 - palockn: psc n autolock when this bit is set, the output compare registers ra, sa, sb, the output matrix po m2 and the psc output con- figuration psocn can be written without disturbing the psc cycles . the update of the psc in ternal registers will be done at the end of the psc cycle if the output compare register rb has been the last written. when set, this bit prevails over lock (bit 5) ? bit 5 ? plockn: psc n lock when this bit is set, the output co mpare registers ra, rb, sa, sb, the ou tput matrix pom2 and the psc output configuration psocn can be written without disturbing the psc cycles. the update of the psc internal registers will be done if the lock bit is released to zero. ? bit 4:3 ? pmoden1: 0: psc n mode select the mode of psc. ? bit 2 ? popn: psc n output polarity if this bit is cleared, the psc outputs are active low. if this bit is set, the psc outputs are active high. ? bit 1 ? pclkseln: psc n input clock select this bit is used to select between clkpf or clkps clocks. set this bit to select th e fast clock input (clkpf). bit 76543210 pfifty1 palock1 plock1 pmode11 pmode10 pop1 pclksel1 - pcnf1 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 pfifty2 palock2 plock2 pmode21 pmode20 pop2 pclksel2 pome2 pcnf2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 15-13. psc n mode selection pmoden1 pmoden0 description 0 0 one ramp mode 01two ramp mode 1 0 four ramp mode 1 1 center aligned mode 157 at90pwm216/316 [datasheet] 7710h?avr?07/2013 clear this bit to select th e slow clock input (clkps). ? bit 0 ? pome2: psc 2 output matrix enable (psc2 only) set this bit to enable the output matrix feature on psc2 outputs. see ?psc2 outputs? on page 150 . when output matrix is used, the psc n output polarity popn has no action on the outputs. 15.25.11 psc 0 control register ? pctl0 ? bit 7:6 ? ppre01:0 : psc 0 prescaler select this two bits select the psc input clock division factor . all generated waveform will be modified by this factor. ? bit 5 ? pbfm0 : balance flank width modulation when this bit is clear, flank width modulation operates on on-time 1 only. when this bit is set, flank width modulation operates on on-time 0 and on-time 1. ? bit 4 ? paoc0b : psc 0 asynchronous output control b when this bit is set, fault input selected to block b can act directly to pscout01 output. see see ?psc input con- figuration? on page 139. . ? bit 3 ? paoc0a : psc 0 asynchronous output control a when this bit is set, fault input selected to block a can act directly to pscout00 output. see see ?psc input con- figuration? on page 139. . ? bit 2 ? parun0 : psc 0 autorun when this bit is set, the psc 0 starts with psc2. that means that psc 0 starts : ? when prun2 bit in pctl2 is set, ? or when parun2 bit in pctl2 is set and prun1 bit in pctl1 register is set. thanks to this bit, 2 or 3 pscs can be synchronized (motor control for example) ? bit 1 ? pccyc0 : psc 0 complete cycle when this bit is set, the psc 0 completes the entire wave form cycle before halt oper ation requested by clearing prun0. this bit is not relevant in slave mode (parun0 = 1). ? bit 0 ? prun0 : psc 0 run writing this bit to one starts the psc 0. bit 76543210 ppre01 ppre00 pbfm0 paoc0b paoc0a parun0 pccyc0 prun0 pctl0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 15-14. psc 0 prescaler selection ppre01 ppre00 description 0 0 no divider on psc input clock 0 1 divide the psc input clock by 4 1 0 divide the psc input clock by 32 1 1 divide the psc clock by 256 158 at90pwm216/316 [datasheet] 7710h?avr?07/2013 when set, this bit prevails over parun0 bit. 15.25.12 psc 1 control register ? pctl1 ? bit 7:6 ? ppre11:0 : psc 1 prescaler select this two bits select the psc input clock division fact or.all generated wave form will be modified by this factor. ? bit 5 ? pbfm1 : balance flank width modulation when this bit is clear, flank width modulation operates on on-time 1 only. when this bit is set, flank width modulation operates on on-time 0 and on-time 1. ? bit 4 ? paoc1b : psc 1 asynchronous output control b when this bit is set, fault input selected to block b can act directly to pscout11 output. see ?psc input configu- ration? on page 139 . ? bit 3 ? paoc1a : psc 1 asynchronous output control a when this bit is set, fault input selected to block a can act directly to pscout10 output. see ?psc input configu- ration? on page 139 . ? bit 2 ? parun1 : psc 1 autorun when this bit is set, the psc 1 starts with psc0. that means that psc 1 starts : ? when prun0 bit in pctl0 register is set, ? or when parun0 bit in pctl0 is set and prun2 bit in pctl2 register is set. thanks to this bit, 2 or 3 pscs can be synchronized (motor control for example) ? bit 1 ? pccyc1 : psc 1 complete cycle when this bit is set, the psc 1 completes the entire wave form cycle before halt oper ation requested by clearing prun1. this bit is not relevant in slave mode (parun1 = 1). ? bit 0 ? prun1 : psc 1 run writing this bit to one starts the psc 1. when set, this bit prevails over parun1 bit. bit 76543210 ppre11 ppre10 pbfm1 paoc1b paoc1a parun1 pccyc1 prun1 pctl1 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 15-15. psc 1 prescaler selection ppre11 ppre10 description 0 0 no divider on psc input clock 0 1 divide the psc input clock by 4 1 0 divide the psc input clock by 32 1 1 divide the psc clock by 256 159 at90pwm216/316 [datasheet] 7710h?avr?07/2013 15.25.13 psc 2 control register ? pctl2 ? bit 7:6 ? ppre21:0 : psc 2 prescaler select this two bits select the psc input clock division fact or.all generated wave form will be modified by this factor. ? bit 5 ? pbfm2 : balance flank width modulation when this bit is clear, flank width modulation operates on on-time 1 only. when this bit is set, flank width modulation operates on on-time 0 and on-time 1. ? bit 4 ? paoc2b : psc 2 asynchronous output control b when this bit is set, fault input se lected to block b can act directly to pscout21 and pscout23 outputs. see section ?psc clock sources?, page 152. ? bit 3 ? paoc2a : psc 2 asynchronous output control a when this bit is set, fault input se lected to block a can act directly to pscout20 and pscout22 outputs. see section ?psc clock sources?, page 152. ? bit 2 ? parun2 : psc 2 autorun when this bit is set, the psc 2 starts with psc1. that means that psc 2 starts : ? when prun1 bit in pctl1 register is set, ? or when parun1 bit in pctl1 is set and prun0 bit in pctl0 register is set. ? bit 1 ? pccyc2 : psc 2 complete cycle when this bit is set, the psc 2 completes the entire wave form cycle before halt oper ation requested by clearing prun2. this bit is not relevant in slave mode (parun2 = 1). ? bit 0 ? prun2 : psc 2 run writing this bit to one starts the psc 2. when set, this bit prevails over parun2 bit. 15.25.14 psc n input a c ontrol register ? pfrcna bit 76543210 ppre21 ppre20 pbfm2 paoc2b paoc2a parun2 pccyc2 prun2 pctl2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 15-16. psc 2 prescaler selection ppre21 ppre20 description 0 0 no divider on psc input clock 0 1 divide the psc input clock by 4 1 0 divide the psc input clock by 32 1 1 divide the psc clock by 256 bit 76543210 pcaena piselna pelevna pfltena prfmna3 prfmna2 prfmna1 prfmna0 pfrcna read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 160 at90pwm216/316 [datasheet] 7710h?avr?07/2013 15.25.15 psc n input b c ontrol register ? pfrcnb the input control registers are used to configure the 2 ps c?s retrigger/fault block a & b. the 2 blocks are iden- tical, so they are configured on the same way. ? bit 7 ? pcaenx : psc n capture enable input part x writing this bit to one enables the capture function when ex ternal event occurs on input selected as input for part x (see piselnx bit in the same register). ? bit 6 ? piselnx : psc n input select for part x clear this bit to select pscinn as input of fault/retrigger block x. set this bit to select comparator n outp ut as input of fault/retrigger block x. ? bit 5 ?pelevnx : psc n edge level selector of input part x when this bit is clear, the falling edge or low level of se lected input generates the significative event for retrigger or fault function . when this bit is set, the rising edge or high level of se lected input generates the sign ificative event for retrigger or fault function. ? bit 4 ? pfltenx : psc n filt er enable on input part x setting this bit (to one) activates the input capture noise canceler. when the noise canceler is activated, the input from the retrigger pin is filtered. the filter function requi res four successive equal valued samples of the retrigger pin for changing its output. the input capture is therefor e delayed by four oscillator cycles when the noise canceler is enabled. ? bit 3:0 ? prfmnx3:0: psc n fault mode these four bits define the mode of operat ion of the fault or retrigger functions. (see psc functional specification for more explanations) table 15-17. level sensitivity and fault mode operation bit 76543210 pcaenb piselnb pelevnb pfltenb prfmnb3 prfmnb2 prfmnb1 prfmnb0 pfrcnb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 prfmnx3:0 description 0000b no action, psc input is ignored 0001b psc input mode 1: stop signal, jump to opposite dead-time and wait 0010b psc input mode 2: stop signal, ex ecute opposite dead-time and wait 0011b psc input mode 3: stop signal, ex ecute opposite while fault active 0100b psc input mode 4: deactivate outputs without changing timing. 0101b psc input mode 5: stop signal and insert dead-time 0110b psc input mode 6: stop signal, jump to opposite dead-time and wait. 0111b psc input mode 7: halt psc and wait for software action 1000b psc input mode 8: edge retrigger psc 1001b psc input mode 9: fixed frequency edge retrigger psc 161 at90pwm216/316 [datasheet] 7710h?avr?07/2013 15.25.16 psc 0 input capture register ? picr0h and picr0l 15.25.17 psc 1 input capture register ? picr1h and picr1l 15.25.18 psc 2 input capture register ? picr2h and picr2l ? bit 7 ? pcstn : psc capture software trig bit set this bit to trigger off a capture of the psc counter. when reading, if this bit is set it means that the capture oper- ation was triggered by pcstn setting otherwise it means th at the capture operation was triggered by a psc input. the input capture is updated with the ps c counter value each time an event occurs on the enabled psc input pin (or optionally on the analog comparator output) if the capt ure function is enabled (bit pcaenx in pfrcnx register is set). the input capture register is 12-bit in size. to ensure that both the high and low bytes are read simultaneously when the cpu accesses these registers, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit or 12-bit registers. 1010b reserved (do not use) 1011b 1100b 1101b 1110b psc input mode 14: fixed frequency edge retrigger psc and disactivate output 1111b reserved (do not use) prfmnx3:0 description bit 76543210 pcst0 ? ? ? picr0[11:8] picr0h picr0[7:0] picr0l read/write rrrrrrrr initial value 00000000 bit 76543210 pcst1 ? ? ? picr1[11:8] picr1h picr1[7:0] picr1l read/write rrrrrrrr initial value 00000000 bit 76543210 pcst2 ? ? ? picr2[11:8] picr2h picr2[7:0] picr2l read/write rrrrrrrr initial value 00000000 162 at90pwm216/316 [datasheet] 7710h?avr?07/2013 15.26 psc2 specific register 15.26.1 psc 2 output matrix ? pom2 ? bit 7 ? pomv2b3: output matrix output b ramp 3 this bit gives the state of the pscout21 (and/or pscout23) during ramp 3 ? bit 6 ? pomv2b2: output matrix output b ramp 2 this bit gives the state of the pscout21 (and/or pscout23) during ramp 2 ? bit 5 ? pomv2b1: output matrix output b ramp 1 this bit gives the state of the pscout21 (and/or pscout23) during ramp 1 ? bit 4 ? pomv2b0: output matrix output b ramp 0 this bit gives the state of the pscout21 (and/or pscout23) during ramp 0 ? bit 3 ? pomv2a3: output matrix output a ramp 3 this bit gives the state of the pscout20 (and/or pscout22) during ramp 3 ? bit 2 ? pomv2a2: output matrix output a ramp 2 this bit gives the state of the pscout20 (and/or pscout22) during ramp 2 ? bit 1 ? pomv2a1: output matrix output a ramp 1 this bit gives the state of the pscout20 (and/or pscout22) during ramp 1 ? bit 0 ? pomv2a0: output matrix output a ramp 0 this bit gives the state of the pscout20 (and/or pscout22) during ramp 0 15.26.2 psc0 interrupt mask register ? pim0 15.26.3 psc1 interrupt mask register ? pim1 15.26.4 psc2 interrupt mask register ? pim2 bit 76543210 pomv2b3 pomv2b2 pomv2b1 pomv2b0 pomv2a3 pomv2a2 pomv2a1 pomv2a0 pom2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 - - pseie0 peve0b peve0a - - peope0 pim0 read/write r r r/w r/w r/w r r r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 - - pseie1 peve1b peve1a - - peope1 pim1 read/write r r r/w r/w r/w r r r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 - - pseie2 peve2b peve2a - - peope2 pim2 read/write r r r/w r/w r/w r r r/w initial value 0 0 0 0 0 0 0 0 163 at90pwm216/316 [datasheet] 7710h?avr?07/2013 ? bit 5 ? pseien : psc n synchro error interrupt enable when this bit is set, the psein bit (if set) generate an interrupt. ? bit 4 ? pevenb : psc n extern al event b interrupt enable when this bit is set, an external event which can genera tes a capture from retrigger/fault block b generates also an interrupt. ? bit 3 ? pevena : psc n extern al event a interrupt enable when this bit is set, an external event which can genera tes a capture from retrigger/fault block a generates also an interrupt. ? bit 0 ? peopen : psc n end of cycle interrupt enable when this bit is set, an interrupt is generated when psc reaches the end of the whole cycle. 15.26.5 psc0 interrupt flag register ? pifr0 15.26.6 psc1 interrupt flag register ? pifr1 15.26.7 psc2 interrupt flag register ? pifr2 ? bit 7 ? poacnb : psc n output b activity this bit is set by hardware each time the outpu t pscoutn1 changes from 0 to 1 or from 1 to 0. must be cleared by software by writing a one to its location. this feature is useful to detect that a psc output d oesn?t change due to a freezen external input signal. ? bit 6 ? poacna : psc n output a activity this bit is set by hardware each time the outpu t pscoutn0 changes from 0 to 1 or from 1 to 0. must be cleared by software by writing a one to its location. this feature is useful to detect that a psc output d oesn?t change due to a freezen external input signal. ? bit 5 ? psein : psc n synchro error interrupt this bit is set by hardware when the update (or end of psc cycle) of the psc n configured in auto run (parunn = 1) does not occur at the same time than the pscn-1 wh ich has generated the input run signal. (for psc0, pscn-1 is psc2). must be cleared by software by writing a one to its location. bit 76543210 poac0b poac0a psei0 pev0b pev0a prn01 prn00 peop2 pifr0 read/write r r r/w r/w r/w r r r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 poac1b poac1a psei1 pev1b pev1a prn11 prn10 peop1 pifr1 read/write r r r/w r/w r/w r r r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 poac2b poac2a psei2 pev2b pev2a prn21 prn20 peop2 pifr2 read/write r r r/w r/w r/w r r r/w initial value 0 0 0 0 0 0 0 0 164 at90pwm216/316 [datasheet] 7710h?avr?07/2013 this feature is useful to detect that a psc doesn?t run at the same speed or with the same phase than the psc master. ? bit 4 ? pevnb : psc n ex ternal event b interrupt this bit is set by hardware when an external event whic h can generates a capture or a retrigger from retrig- ger/fault block b occurs. must be cleared by software by writing a one to its location. this bit can be read even if the corresponding in terrupt is not enabled (pevenb bit = 0). ? bit 3 ? pevna : psc n ex ternal event a interrupt this bit is set by hardware when an external event whic h can generates a capture or a retrigger from retrig- ger/fault block a occurs. must be cleared by software by writing a one to its location. this bit can be read even if the corresponding in terrupt is not enabled (pevena bit = 0). ? bit 2:1 ? prnn1:0 : psc n ramp number memorization of the ramp number when the last pevna or pevnb occured . ? bit 0 ? peopn: end of psc n interrupt this bit is set by hardware when psc n achieves its whole cycle. must be cleared by software by writing a one to its location. table 15-18. psc n ramp numb er description prnn1 prnn0 description 0 0 the last event which has generated an interrupt occured during ramp 1 0 1 the last event which has generated an interrupt occured during ramp 2 1 0 the last event which has generated an interrupt occured during ramp 3 1 1 the last event which has generated an interrupt occured during ramp 4 165 at90pwm216/316 [datasheet] 7710h?avr?07/2013 16. serial peripheral interface ? spi the serial peripheral interface (spi) allows high-speed synchronous data transfer between the at90pwm216/316 and peripheral devices or between several avr devices. the at90pwm216/316 spi includes the following features: 16.1 features ? full-duplex, three-wire synchronous data transfer ? master or slave operation ? lsb first or msb first data transfer ? seven programmable bit rates ? end of transmission interrupt flag ? write collision flag protection ? wake-up from idle mode ? double speed (ck/2) master spi mode figure 16-1. spi block diagram (1) note: 1. refer to figure 2-1 on page 2 , and table 10-3 on page 63 for spi pin placement. the interconnection between master a nd slave cpus with spi is shown in figure 16-2 . the system consists of two shift registers, and a master clock generator. the spi ma ster initiates the communica tion cycle when pulling low the slave select ss pin of the desired slave. master and slave prepar e the data to be sent in their respective shift registers, and the master generates the required clock pulses on the sck line to interchange data. data is always spi2x spi2x divider /2/4/8/16/32/64/128 clk io miso miso _a mosi mosi _a sck sck _a ss ss_a spips 166 at90pwm216/316 [datasheet] 7710h?avr?07/2013 shifted from master to slave on the master out ? slave in, mosi, line, and from slave to master on the master in ? slave out, miso, line. after each data packet, the master will synchronize the slave by pulling high the slave select, ss , line. when configured as a master, the spi inte rface has no automatic control of the ss line. this must be handled by user software before communication can st art. when this is done, writing a byte to the spi data register starts the spi clock generator, and the hardware shif ts the eight bits into the slave. afte r shifting one byte, the spi clock gen- erator stops, setting the end of transm ission flag (spif). if the spi interrupt enable bit ( spie) in the spcr register is set, an interrupt is requested. the mast er may continue to shift the next byte by writing it into spdr, or signal the end of packet by pulling high the slave select, ss line. the last incoming byte will be kept in the buffer register for later use. when configured as a slave, the spi interface will remain sleeping with miso tri-stated as long as the ss pin is driven high. in this state, software may update the cont ents of the spi data regist er, spdr, but the data will not be shifted out by incoming clock pulses on the sck pin until the ss pin is driven low. as one byte has been com- pletely shifted, the end of transmission flag, spif is set. if the spi interrup t enable bit, spie, in the spcr register is set, an interrupt is requested. the slave may continue to place new data to be sent into spdr before reading the incoming data. the last in coming byte will be kept in the buffer register for later use. figure 16-2. spi master-slave interconnection the system is single buffered in the transmit direction and double buffered in the receive direction. this means that bytes to be transmitted cannot be written to the spi data register before the entire shift cycle is completed. when receiving data, however, a received character must be read from the spi data register before the next character has been completely shifted in. ot herwise, the first byte is lost. in spi slave mode, the control logic w ill sample the incoming si gnal of the sck pin. to ensure correc t sampling of the clock signal, the frequency of the spi clock should never exceed f clkio /4. when the spi is enabled, the data direction of the mosi, miso, sck, and ss pins is overridden according to table 16-1 . for more details on automatic port overrides, refer to ?alternate port functions? on page 61 . table 16-1. spi pin overrides (1) pin direction, master spi direction, slave spi mosi user defined input miso input user defined sck user defined input ss user defined input shift enable 167 at90pwm216/316 [datasheet] 7710h?avr?07/2013 note: 1. see ?alternate functions of port b? on page 63 for a detailed description of how to define the direction of the user defined spi pins. the following code examples show how to initialize the spi as a master and how to perform a simple transmission. ddr_spi in the examples must be re placed by the actual data directio n register controlling the spi pins. dd_mosi, dd_miso and dd_sck must be replaced by the actu al data direction bits fo r these pins. e.g. if mosi is placed on pin pb2, replace dd_mo si with ddb2 and ddr_spi with ddrb. note: 1. the example code assumes that the part specific header file is included. the following code examples show how to initialize the spi as a slave and how to perform a simple reception. table 2. assembly code example (1) spi_masterinit: ; set mosi and sck output, all others input ldi r17,(1< 170 at90pwm216/316 [datasheet] 7710h?avr?07/2013 ? bit 6 ? spe: spi enable when the spe bit is written to one, the spi is enable d. this bit must be set to enable any spi operations. ? bit 5 ? dord: data order when the dord bit is written to one, the lsb of the data word is transmitted first. when the dord bit is written to zero, the msb of the data word is transmitted first. ? bit 4 ? mstr: master/slave select this bit selects master spi mode when written to one, and slave spi mode when written logic zero. if ss is config- ured as an input and is driven low while mstr is se t, mstr will be cleared, and sp if in spsr will become set. the user will then have to set mstr to re-enable spi master mode. ? bit 3 ? cpol: clock polarity when this bit is written to one, sck is high when idle. when cpol is written to zero, sck is low when idle. refer to figure 16-3 and figure 16-4 for an example. the cpol functionality is summarized below: ? bit 2 ? cpha: clock phase the settings of the clock phase bit (cpha) determine if data is sampled on the leading (first) or trailing (last) edge of sck. refer to figure 16-3 and figure 16-4 for an example. the cpol functionality is summarized below: ? bits 1, 0 ? spr1, spr0: spi clock rate select 1 and 0 these two bits control the sck rate of the device confi gured as a master. spr1 and spr0 have no effect on the slave. the relationship between sck and the clk io frequency f clkio is shown in the following table: table 16-2. cpol functionality cpol leading edge trailing edge 0 rising falling 1 falling rising table 16-3. cpha functionality cpha leading edge trailing edge 0 sample setup 1 setup sample table 16-4. relationship between sck an d the oscillator frequency spi2x spr1 spr0 sck frequency 000 f clkio / 4 001 f clkio / 16 010 f clkio / 64 011 f clkio / 128 100 f clkio / 2 101 f clkio / 8 110 f clkio / 32 111 f clkio / 64 171 at90pwm216/316 [datasheet] 7710h?avr?07/2013 16.2.5 spi status register ? spsr ? bit 7 ? spif: spi interrupt flag when a serial transfer is complete, the spif flag is set. an interrupt is generated if spie in spcr is set and global interrupts are enabled. if ss is an input and is driven low when the spi is in master mode, this will also set the spif flag. spif is cleared by hardware w hen executing the corresponding interrupt handling vector. alternatively, the spif bit is cleared by first reading the spi status register with spif set, then accessing the spi data register (spdr). ? bit 6 ? wcol: write collision flag the wcol bit is set if the spi data re gister (spdr) is written during a data transfer. the wcol bit (and the spif bit) are cleared by first reading the spi status register with wcol set, and then accessing the spi data register. ? bit 5..1 ? res: reserved bits these bits are reserved bits in the at90pwm2 16/316 and will always read as zero. ? bit 0 ? spi2x: double spi speed bit when this bit is written logic one the spi speed (sck frequency) will be doubled when the spi is in master mode (see table 16-4 ). this means that the minimum sck period will be two cpu clock periods. when the spi is config- ured as slave, the spi is only guaranteed to work at f clkio /4 or lower. the spi interface on the at90pwm216/316 is also us ed for program memory and eeprom downloading or uploading. see serial programming algorithm279 for serial programming and verification. 16.2.6 spi data register ? spdr ? bits 7:0 - spd7:0: spi data the spi data register is a read/write register used for data transfer between the register file and the spi shift register. writing to the regist er initiates data transmission . reading the register causes the shift register receive buffer to be read. 16.3 data modes there are four combinations of sck phase and polarity with respect to serial data, wh ich are determined by control bits cpha and cpol. the spi data transfer formats are shown in figure 16-3 and figure 16-4 . data bits are shifted out and latched in on opposite edges of the sck signal, ensuring sufficient ti me for data signals to stabilize. bit 76543210 spifwcol?????spi2xspsr read/write rrrrrrrr/w initial value 00000000 bit 76543210 spd7 spd6 spd5 spd4 spd3 spd2 spd1 spd0 spdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value xxxxxxxxu ndefined 172 at90pwm216/316 [datasheet] 7710h?avr?07/2013 this is clearly seen by summarizing table 16-2 and table 16-3 , as done below: figure 16-3. spi transfer format with cpha = 0 figure 16-4. spi transfer format with cpha = 1 table 16-5. cpol functionality leading edge trailing edge spi mode cpol=0, cpha=0 sample (rising) setup (falling) 0 cpol=0, cpha=1 setup (rising) sample (falling) 1 cpol=1, cpha=0 sample (falling) setup (rising) 2 cpol=1, cpha=1 setup (falling) sample (rising) 3 bit 1 bit 6 lsb msb sck (cpol = 0) mode 0 sample i mosi/miso change 0 mosi pin change 0 miso pin sck (cpol = 1) mode 2 ss msb lsb bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 msb first (dord = 0) lsb first (dord = 1) sck (cpol = 0) mode 1 sample i mosi/miso change 0 mosi pin change 0 miso pin sck (cpol = 1) mode 3 ss msb lsb bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 lsb msb msb first (dord = 0) lsb first (dord = 1) 173 at90pwm216/316 [datasheet] 7710h?avr?07/2013 17. usart the universal synchronous and asynchronous serial receiv er and transmitter (usart) is a highly flexible serial communication device. the main features are: 17.1 features ? full duplex operation (independent serial receive and transmit registers) ? asynchronous or synchronous operation ? master or slave clocked synchronous operation ? high resolution baud rate generator ? supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits ? odd or even parity generation and parity check supported by hardware ? data overrun detection ? framing error detection ? noise filtering includes false start bi t detection and digital low pass filter ? three separate interrupts on tx complete , tx data register empty and rx complete ? multi-processor communication mode ? double speed asynchronous communication mode ? usart extended mode (eusart) with: ? independant bit number configuration for transmit and receive ? supports serial frames with 5, 6, 7, 8, 9 or 13, 14, 15, 16, 17 data bits and 1 or 2 stop bits ? biphase manchester encode/decoder (for dali communications) ? manchester framing error detection ? bit ordering configuration (msb or lsb first) ? sleep mode exit under re ception of eusart frame 17.2 overview a simplified block diagram of th e usart transmitter is shown in figure 17-1 . cpu accessible i/o registers and i/o pins are shown in bold. 174 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 17-1. usart block diagram (1) note: 1. refer to pin configurations2 , table 10-9 on page 68 , and table 10-7 on page 67 for usart pin placement. the dashed boxes in the block diagram separate the three main parts of th e usart (listed from the top): clock generator, transmitter and receiver. cont rol registers are shared by all units. the clock generation logic consists of synchronization logic for external clock input used by synchronous slave operation, and the baud rate generator. the xck (transfer clock) pin is only used by synchronous transfer mode. the transmitter consists of a single write buffer, a serial shift register, parity generator and control logic for handling different serial frame formats. the write buffer allows a continuous transfer of data without any delay between frames. the receiver is the most complex part of the usart module due to its clock and da ta recovery units. the reco very units are used for asyn- chronous data reception. in addition to the recovery units, the receiver includes a parity checker, control logic, a shift register and a two level receive buffer (udr). the receiver supports the same frame formats as the trans- mitter, and can detect frame error, data overrun and parity errors. 17.3 clock generation the clock generation logic generates the base clock for the transmitter and receiver. the usart supports four modes of clock operation: normal asynchronous, double speed asynchronous, master synchronous and slave synchronous mode. the umsel bit in usart control and status register c (ucsrc) selects between asynchro- nous and synchronous operation. double speed (asynchronous mode only) is controlled by the u2x found in the ucsra register. when using synchronous mode (umsel = 1), the data direction register for the xck pin parity generator ubrr[h:l] udr (transmit) ucsra ucsrb ucsrc baud rate generator transmit shift register receive shift register rxd txd pin control udr (receive) pin control xck data recovery clock recovery pin control tx control rx control parity checker data bus clkio sync logic clock generator transmitter receiver 175 at90pwm216/316 [datasheet] 7710h?avr?07/2013 (ddr_xck) controls whether the clock source is internal (master mode) or external (slave mode). the xck pin is only active when using synchronous mode. figure 17-2 shows a block diagram of the clock generation logic. figure 17-2. usart clock generation logic, block diagram signal description: txn clk transmitter clock (internal signal). rxn clk receiver base clock (internal signal). xn cki input from xck pin (internal signal). used for synchronou s slave operation. xn cko clock output to xck pin (internal si gnal). used for synchronous master operation. f clk io system i/o clock frequency. 17.3.1 internal clock genera tion ? baud rate generator internal clock generation is used for the asynchronous and the synchronous master modes of operation. the description in this section refers to figure 17-2 . the usart baud rate register (ubrr) and the down-count er connected to it function as a programmable pres- caler or baud rate generator. the down-counter, running at system clock ( f clk io ), is loaded with the ubrr value each time the counter has counted down to zero or when the ubrrl register is writte n. a clock is generated each time the counter reaches zero . this clock is the baud rate generator clock output (= f clk io /(ubrr+1)). the trans- mitter divides the baud rate generat or clock output by 2, 8 or 16 depe nding on mode. the baud rate generator output is used directly by the receiver?s clock and data recovery units. however, the recovery units use a state machine that uses 2, 8 or 16 states depending on m ode set by the state of the umsel, u2x and ddr_xck bits. prescaling down-counter /2 ubrrn /4 /2 f clk ubrrn+1 sync register clk xckn pin txn clk u2xn umseln ddr_xckn 0 1 0 1 xn cki xn cko ddr_xckn rxn clk 0 1 1 0 edge detector ucpoln io io 176 at90pwm216/316 [datasheet] 7710h?avr?07/2013 table 17-1 contains equations for calculating the baud rate (in bits per second) and for calculating the ubrr value for each mode of operation using an internally generated clock source. note: 1. the baud rate is defined to be the transfer rate in bit per second (bps) baud baud rate (in bits per second, bps). f clk io system i/o clock frequency. ubrr contents of the ubrrh and ubrrl registers, (0-4095). some examples of ubrr values for some system clock frequencies are found in table 17-9 (see page 196 ). 17.3.2 double speed operation (u2x) the transfer rate can be doubled by setting the u2x bit in ucsra. setting this bit only has effect for the asynchro- nous operation. set this bit to zero when using synchronous operation. setting this bit will reduce the divisor of the baud rate divider from 16 to 8, e ffectively doubling the transfer rate for asynchronous communication. note however that the receiver will in this case only use half the number of sam- ples (reduced from 16 to 8) for data sampling and clock recovery, and therefore a more accurate baud rate setting and system clock are required when this mode is used. for the transmitter, there are no downsides. 17.3.3 external clock external clocking is used by the sync hronous slave modes of operation. the des cription in this section refers to figure 17-2 for details. external clock input from the xck pin is sampled by a synch ronization register to minimize the chance of meta-sta- bility. the output from the synchronization register must then pass through an edge detector before it can be used by the transmitter and receiver. this process introduc es a two cpu clock period delay and therefore the maxi- mum external xck clock frequency is limited by the following equation: note that f clk io depends on the stability of the system clock sour ce. it is therefore reco mmended to add some mar- gin to avoid possible loss of data due to frequency variations. 17.3.4 synchronous clock operation when synchronous mode is used (umsel = 1), the xck pin will be used as eith er clock input (slave) or clock out- put (master). the dependency between the clock edges and data sampling or data change is the same. the basic table 17-1. equations for calculating ba ud rate register setting operating mode equation for calculating baud rate (1) equation for calculating ubrr value asynchronous normal mode (u2x = 0) asynchronous double speed mode (u2x = 1) synchronous master mode baud f clkio 16 ubrr n 1 + ?? ----------------------------------------- - = ubrr n f clkio 16 baud ----------------------- - 1 ? = baud f clkio 8 ubrr n 1 + ?? -------------------------------------- - = ubrr n f clkio 8 baud -------------------- 1 ? = baud f clkio 2 ubrr n 1 + ?? -------------------------------------- - = ubrr n f clkio 2 baud -------------------- 1 ? = f xckn f clkio 4 --------------- - ? 177 at90pwm216/316 [datasheet] 7710h?avr?07/2013 principle is that data input (on rxd) is sampled at t he opposite xck clock edge of the edge the data output (txdn) is changed. figure 17-3. synchronous mode xck timing. the ucpol bit ucrsnc selects which xck clock edge is used for data sampling and which is used for data change. as figure 17-3 shows, when ucpol is zero the data will be changed at rising xc k edge and sampled at falling xck edge. if ucpol is set, the data will be changed at falling xck edge and sa mpled at rising xck edge. 17.4 serial frame a serial frame is defined to be one char acter of data bits with sync hronization bits (start an d stop bits), and option- ally a parity bit for error checking. 17.4.1 frame formats the usart accepts all 30 combinations of the following as va lid frame formats: ? 1 start bit ? 5, 6, 7, 8, or 9 data bits ? no, even or odd parity bit ? 1 or 2 stop bits a frame starts with the start bit followed by the least si gnificant data bit. then the next data bits, up to a total of nine, are succeeding, ending with the most significant bit. if enabl ed, the parity bit is in serted after the data bits, before the stop bits. when a complete frame is transmitted, it can be directly followed by a new frame, or the com- munication line can be set to an idle (high) state. figure 17-4 illustrates the possible combinations of the frame formats. bits inside brackets are optional. figure 17-4. frame formats st start bit, always low. (n) data bits (0 to 8). p parity bit. can be odd or even. sp stop bit, always high. rxdn / txdn xckn rxdn / txdn xckn ucpoln = 0 ucpoln = 1 sample sample 1 0 2 3 4 [5] [6] [7] [8] [p] st sp1 [sp2] (st / idle) (idle) frame 178 at90pwm216/316 [datasheet] 7710h?avr?07/2013 idle no transfers on the communication line (rxd or txd). an idle line must be high. the frame format used by the usart is set by the ucsz2:0, upm1:0 and usbs bits in ucsrb and ucsrc. the receiver and transmitter use the same setting. note that changing the setting of any of these bits will corrupt all ongoing communication for both the receiver and transmitter. the usart character size (ucsz2:0) bi ts select the number of data bits in the frame. the usart parity mode (upm1:0) bits enable and set the type of parity bit. the selection between one or two stop bits is done by the usart stop bit select (usbs) bit. the receiver ignores the second stop bit. an fe (frame error) will therefore only be detected in the cases wh ere the first stop bit is zero. 17.4.2 parity bit calculation the parity bit is calculated by doing an ex clusive-or of all the data bits. if odd pa rity is used, the result of the exclu- sive or is inverted. the relation between the parity bit and data bits is as follows: p even parity bit using even parity p odd parity bit using odd parity d n data bit n of the character if used, the parity bit is located between the last data bit and first stop bit of a serial frame. 17.5 usart initialization the usart has to be initialized before any communication can take place. the configuration between the usart or eusart mode should be done before any other configuration. the initialization process normally consists of setting the baud rate, setting frame format and enabling the trans- mitter or the receiver depending on the usage. for interrupt driven usart operation, the global interrupt flag should be cleared (and interrupts globally disabled) when doing the initialization. before doing a re-initialization with changed baud rate or frame format, be sure that there are no ongoing transmis- sions during the period the registers are changed. the txc flag can be used to check that the transmitter has completed all transfers, and the rxc flag can be used to ch eck that there are no unread data in the receive buffer. note that the txc flag must be cleared before each tran smission (before udr is written) if it is used for this purpose. the following simple usart initializat ion code examples show one assembly and one c function that are equal in functionality. the examples assume asynchronous operation using po lling (no interrupts e nabled) and a fixed frame format. the baud rate is given as a function parameter. for the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers. p even d n 1 ? ? d 3 d 2 d 1 d 0 0 p odd ?????? d n 1 ? ? d 3 d 2 d 1 d 0 1 ?????? = = 179 at90pwm216/316 [datasheet] 7710h?avr?07/2013 note: 1. the example code assumes that the part specific header file is included. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?c bi?, and ?sbi? instructions must be replaced with instructions that allo w access to extended i/o. typically ?lds? and ?sts? combined with ?sbrs?, ?sbrc?, ?sbr?, and ?cbr?. more advanced initialization routines can be made that include frame format as parameters, disable interrupts and so on. however, many applications use a fixed setting of the baud and control registers, and for these types of applications the initialization code can be placed directly in the main rout ine, or be combined with initialization code for other i/o modules. 17.6 data transmission ? usart transmitter the usart transmitter is enabled by setting the transmit enable (txen) bit in the ucsrb register. when the transmitter is enabled, the normal port operation of the txdn pin is overridden by the usart and given the func- tion as the transmitter?s se rial output. the baud rate, mode of operation and frame format must be set up once before doing any transmissions. if syn chronous operation is used, the cl ock on the xck pin will be overridden and used as transmission clock. 17.6.1 sending frames with 5 to 8 data bit a data transmission is initiated by load ing the transmit buffer with the data to be transmitted. the cpu can load the transmit buffer by wr iting to the udr i/o location. th e buffered data in the transmit buffer will be moved to the shift register when the shift register is ready to send a new fram e. the shift register is loaded with new data if it is in idle state (no ongoing transmission) or immediately after the last stop bit of the previous frame is transmitted. when assembly code example (1) usart_init: ; set baud rate sts ubrrh, r17 sts ubrrl, r16 ; set frame format: 8data, no parity & 2 stop bits ldi r16, (0< 183 at90pwm216/316 [datasheet] 7710h?avr?07/2013 note: 1. the example code assumes that the part specific header file is included. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?c bi?, and ?sbi? instructions must be replaced with instructions that allo w access to extended i/o. typically ?lds? and ?sts? combined with ?sbrs?, ?sbrc?, ?sbr?, and ?cbr?. the function simply waits for data to be present in the receive buffer by checking the rxc flag, before reading the buffer and returning the value. 17.7.2 receiving frames with 9 data bits if 9-bit characters are used (ucsz=7) the ninth bit must be read from the rxb8 bit in ucsrb before reading the low bits from the udr. this rule a pplies to the fe, dor and upe status fl ags as well. read st atus from ucsra, then data from udr. reading the udr i/o location will change the state of the receive buffer fifo and conse- quently the txb8, fe, dor and upe bits, which all are stored in the fifo, will change. the following code example shows a simple usart receive function that handles both nine bit characters and the status bits. assembly code example (1) usart_receive: ; wait for data to be received sbis ucsra, rxc rjmp usart_receive ; get and return received data from buffer lds r16, udr ret c code example (1) unsigned char usart_receive( void ) { /* wait for data to be received */ while ( !(ucsra & (1< 185 at90pwm216/316 [datasheet] 7710h?avr?07/2013 the receive function example reads all the i/o registers in to the register file befo re any comput ation is done. this gives an optimal receive buffer utilization since the bu ffer location read will be free to accept new data as early as possible. 17.7.3 receive complete flag and interrupt the usart receiver has one flag th at indicates the receiver state. the receive complete (rxc) flag indicates if there are unr ead data present in the receive buffer. this flag is one when unread data exist in the receive buffer, and zero w hen the receive buffer is empty (i.e., does not contain any unread data). if the receiver is disa bled (rxen = 0), the receive buffer w ill be flushed and consequently the rxc bit will become zero. when the receive complete interrupt enable (rxcie) in ucsrb is set, the usart receive complete interrupt will be executed as long as the rxc flag is set (provided that glo bal interrupts are enabled). when interrupt-driven data reception is used, the receive complete routine must read the received data from udr in order to clear the rxc flag, otherwise a new interrupt will oc cur once the interrupt routine terminates. 17.7.4 receiver error flags the usart receiver has three error flags: frame error (fe), data overrun (dor) and parity error (upe). all can be accessed by reading ucsra. common for the error flags is that they are located in the receive buffer together with the frame for which they indicate the error status. due to the buffering of the error flags, the ucsra must be read before the receive buff er (udr), since reading the udr i/o lo cation changes the buffer read location. another equality for the error flags is that they can not be altered by software doing a write to the flag location. however, all flags must be set to zero when the ucsra is written for upward compatib ility of future usart imple- mentations. none of the error flags can generate interrupts. the frame error (fe) flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer. the fe flag is zero when the stop bit was correctly read (as one), and the fe flag will be one when the stop bit was incorrect (zero). this flag can be used for detect ing out-of-sync conditions, detecting break conditions and protocol handling. the fe flag is not affected by the setting of the usbs bi t in ucsrc since th e receiver ignores all, except for the first, stop bits. fo r compatibility with future devices, alwa ys set this bit to zero when writing to ucsra. the data overrun (dor) flag indicates data loss due to a receiver buffer full condition. a data overrun occurs when the receive buffer is full (two ch aracters), it is a new character waitin g in the receive shift register, and a new start bit is detected. if the dor flag is set there was one or more serial frame lost between the frame last read from udr, and the next frame read from udr. for compatib ility with future devices, always write this bit to zero when writing to ucsra. the dor flag is cleared when the frame received was successfully moved from the shift register to the receive buffer. the following example (see figure 17-5.) represents a data overrun condition. as the receive buffer is full with ch1 and ch2, ch3 is lost. when a data overrun condition is det ected, the overrun erro r is memorized. when the two characters ch1 and ch2 are read from the receiv e buffer, the dor bit is set (and not before) and rxc remains set to warn the application about the overrun error. 186 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 17-5. data overrun example the parity error (upe) flag indicates that the next frame in the receive buffer had a parity error when received. if parity check is not enabled the upe bi t will always be read ze ro. for compatibility with fu ture devices, always set this bit to zero when writing to ucsra. for more details see ?parity bit calculation? on page 178 and ?parity checker? on page 186 . 17.7.5 parity checker the parity checker is active when the high usart parity mode (upm1) bit is set. type of parity check to be per- formed (odd or even) is selected by the upm0 bit. when enabled, the parity checker calculates the parity of the data bits in incoming frames and compares the result wit h the parity bit from the serial frame. the result of the check is stored in the receive buffer together with the rece ived data and stop bits. the parity error (upe) flag can then be read by softwar e to check if the fram e had a parity error. the upe bit is set if the next characte r that can be read from the receive buff er had a parity error when received and the parity checking was enabled at that point (upm1 = 1). this bit is valid until the receive buffer (udr) is read. 17.7.6 disabling the receiver in contrast to the transmitter, disab ling of the receiver will be immediate. data from ongoing receptions will there- fore be lost. when disa bled (i.e., the rxen is set to zero) the receiver will no longer override the normal function of the rxd port pin. the rece iver buffer fifo will be flushed when the re ceiver is disabled. re maining data in the buffer will be lost 17.7.7 flushing the receive buffer the receiver buffer fifo will be flushed when the re ceiver is disabled, i.e., the bu ffer will be emptied of its con- tents. unread data will be lost. if the buffer has to be flushed during normal operation, due to for instance an error condition, read the udr i/o location until the rxc flag is cleared. the following code example shows how to flush the receive buffer. ch1 ch2 ch3 rxd rxc dor t software access to receive buffer rxc=1 udr=ch1 dor=0 rxc=1 udr=ch2 dor=0 rxc=1 udr=xx dor=1 187 at90pwm216/316 [datasheet] 7710h?avr?07/2013 note: 1. the example code assumes that the part specific header file is included. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?c bi?, and ?sbi? instructions must be replaced with instructions that allo w access to extended i/o. typically ?lds? and ?sts? combined with ?sbrs?, ?sbrc?, ?sbr?, and ?cbr?. 17.8 asynchronous data reception the usart includes a clock recovery and a data recove ry unit for handling asynchronous data reception. the clock recovery logic is used for synchronizing the internal ly generated baud rate clo ck to the incoming asynchro- nous serial frames at the rxd pin. the data recovery lo gic samples and low pass filters each incoming bit, thereby improving the noise immunity of the receiver. the asynchronous reception operational range depends on the accuracy of the internal baud rate clock, the rate of the incoming frames, and the frame size in number of bits. 17.8.1 asynchronous clock recovery the clock recovery logic sync hronizes internal clock to the incoming serial frames. figure 17-6 illustrates the sam- pling process of the start bit of an incoming frame. the sample rate is 16 times the baud rate for normal mode, and eight times the baud rate for double speed mode. the horiz ontal arrows illustrate the synchronization variation due to the sampling process. note the larger time variation when using the double speed mode (u2x = 1) of oper- ation. samples denoted zero are samples done when th e rxd line is idle (i.e., no communication activity). figure 17-6. start bit sampling when the clock recovery logic detects a high (idle) to lo w (start) transition on the rxd line, the start bit detection sequence is initiated. let sample 1 denote the first zero-sample as shown in the figure. the clock recovery logic then uses samples 8, 9, and 10 for normal mode, and sa mples 4, 5, and 6 for double speed mode (indicated with sample numbers inside boxes on the figure), to decide if a va lid start bit is received. if two or more of these three samples have logical high levels (the majority wins), t he start bit is rejected as a noise spike and the receiver assembly code example (1) usart_flush: sbis ucsra, rxc0 ret lds r16, udr rjmp usart_flush c code example (1) void usart_flush( void ) { unsigned char dummy; while ( ucsra & (1< 189 at90pwm216/316 [datasheet] 7710h?avr?07/2013 the following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate. d sum of character size and parity size (d = 5 to 10 bit) s samples per bit. s = 16 for normal speed mode and s = 8 for double speed mode. s f first sample number used for majority voting. s f = 8 for normal speed and s f = 4 for double speed mode. s m middle sample number used for majority voting. s m = 9 for normal speed and s m = 5 for double speed mode. r slow is the ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate. r fas t is the ratio of the fastest incoming data ra te that can be accepted in relation to the receiver baud rate. table 17-2 and table 17-3 list the maximum receiver baud rate erro r that can be tolerat ed. note that normal speed mode has higher toleration of baud rate variations. table 1. table 17-2. recommended maximum receiver baud rate error for normal speed mode (u2x = 0) d # (data+parity bit) r slow (%) r fast (%) max total error (%) recommended max receiver error (%) 5 93.20 106.67 +6.67/-6.8 3.0 6 94.12 105.79 +5.79/-5.88 2.5 7 94.81 105.11 +5.11/-5.19 2.0 8 95.36 104.58 +4.58/-4.54 2.0 9 95.81 104.14 +4.14/-4.19 1.5 10 96.17 103.78 +3.78/-3.83 1.5 table 17-3. recommended maximum receiver baud rate error for double speed mode (u2x = 1) d # (data+parity bit) r slow (%) r fast (%) max total error (%) recommended max receiver error (%) 5 94.12 105.66 +5.66/-5.88 2.5 6 94.92 104.92 +4.92/-5.08 2.0 7 95.52 104,35 +4.35/-4.48 1.5 8 96.00 103.90 +3.90/-4.00 1.5 9 96.39 103.53 +3.53/-3.61 1.5 10 96.70 103.23 +3.23/-3.30 1.0 r slow d 1 + ?? s s 1 ? ds ? s f ++ ------------------------------------------ - = r fast d 2 + ?? s d 1 + ?? ss m + ----------------------------------- = 190 at90pwm216/316 [datasheet] 7710h?avr?07/2013 the recommendations of the maximum receiver baud rate error was made under the assumption that the receiver and transmitter equally divides the maximum total error. there are two possible sources for the receivers baud rate error. the receiver?s system clock (xtal) will always have some minor instability over the supply voltage range and th e temperature range. when using a crystal to gen- erate the system clock, this is rare ly a problem, but for a resonator the system clock may differ more than 2% depending of the resonators tolerance. the second source for the error is more controllable. the baud rate gener- ator can not always do an exact division of the system fr equency to get the baud rate wanted. in this case an ubrr value that gives an acceptable low error can be used if possible. 17.9 multi-processor communication mode this mode is available only in usart mode, not in eusart. setting the multi-processor communication mode (mpcm) bi t in ucsra enables a filter ing function of incoming frames received by the usart receiv er. frames that do not contain addr ess information will be ignored and not put into the receive buffer. this effectively reduces the number of incoming frames that has to be handled by the cpu, in a system with multip le mcus that communicate via the same se rial bus. the transmitter is unaffected by the mpcm setting, but has to be used differently when it is a part of a sys tem utilizing the mult i-processor commu- nication mode. 17.9.1 mpcm protocol if the receiver is set up to receive frames that contain 5 to 8 data bits, then the first st op bit indicates if the frame contains data or address information. if the receiver is set up for frames with nine data bits, then the ninth bit (rxb8) is used for identifying address and data frames. w hen the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. when the frame type bit is zero the frame is a data frame. the multi-processor communication mode enables several slave mcus to receive data from a master mcu. this is done by first decoding an address frame to find out which mcu has been addressed. if a particular slave mcu has been addressed, it will re ceive the following data fram es as normal, while the ot her slave mcus will ignore the received frames until another address frame is received. 17.9.2 using mpcm for an mcu to act as a master mcu, it can use a 9-bit character frame format (ucsz = 7). the ninth bit (txb8) must be set when an address frame (txb8 = 1) or cleare d when a data frame (txbn = 0) is being transmitted. the slave mcus must in this case be set to use a 9-bit character frame format. the following procedure should be used to exchange data in multi-processor communication mode: 1. all slave mcus are in multi-processor communication mode (mpcm in ucsra is set). 2. the master mcu sends an address frame, and all slav es receive and read this frame. in the slave mcus, the rxc flag in ucsra will be set as normal. 3. each slave mcu reads the udr register and determi nes if it has been selected. if so, it clears the mpcm bit in ucsra, otherwise it waits for the next address byte and keeps the mpcm setting. 4. the addressed mcu will receive all data frames unt il a new address frame is received. the other slave mcus, which still have the mpcm bit set, will ignore the data frames. 5. when the last data frame is received by the addressed mcu, the addressed mcu sets the mpcm bit and waits for a new address frame from master. the process then repeats from 2. using any of the 5- to 8-bit character frame formats is possible, but impractical since the receiver must change between using n and n+1 character fram e formats. this makes full-duplex ope ration difficult since the transmitter and receiver use the same character size setting. if 5- to 8-bit character frames are used, the transmitter must be set to use two stop bit (usbs = 1) since the first stop bit is used for indi cating the frame type. 191 at90pwm216/316 [datasheet] 7710h?avr?07/2013 17.10 usart regist er description 17.10.1 usart i/o data register ? udr ? bit 7:0 ? rxb7:0: receive data buffer (read access) ? bit 7:0 ? txb7:0: transmit data buffer (write access) the usart transmit data buffer regi ster and usart receive data buffer registers share the same i/o address referred to as usart data register or udr. the transmit data buffer register (txbn) will be the destination for data written to the udr register loca tion. reading the udr register locati on will return the contents of the receive data buffer register (rxbn). for 5-, 6-, or 7-bit characters the upper unused bits wi ll be ignored by the transmitter and set to zero by the receiver. the transmit buffer can only be written when the udre flag in the ucsra register is set. data written to udr when the udre flag is not set, will be ignored by the usart transmitter. when data is wr itten to the transmit buf- fer, and the transmitter is enabled, the transmitter will load the data into the transmit shift register when the shift register is empty. then the data will be serially transmitted on the txdn pin. the receive buffer consists of a tw o level fifo. the fifo will change its state whenever the receive buffer is accessed. this register is available in both usart and eusart modes. 17.10.2 usart control and status register a ? ucsra ? bit 7 ? rxc: usart receive complete this flag bit is set when there are unread data in the re ceive buffer and cleared when the receive buffer is empty (i.e., does not contain any unread data). if the receiver is disabled, the receive buffer will be flushed and conse- quently the rxc bit will become zero. the rxc flag can be used to generate a receive complete interrupt (see description of the rxcie bit). this bit is available in both usart and eusart modes. ? bit 6 ? txc: usart transmit complete this flag bit is set when the entire frame in the transmit shift register has been shifted out and there are no new data currently present in the transmit buffer (udr). the txc flag bit is automatically cleared when a transmit com- plete interrupt is executed, or it can be cleared by writing a one to its bit location. the txc flag can generate a transmit complete in terrupt (see description of the txcie bit). this bit is available in both usart and eusart modes. bit 76543210 rxb[7:0] udr (read) txb[7:0] udr (write) read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 rxc txc udre fe dor upe u2x mpcm ucsra read/write r r/w rrrrr/wr/w initial value00100000 192 at90pwm216/316 [datasheet] 7710h?avr?07/2013 ? bit 5 ? udre: usart data register empty the udre flag indicates if the trans mit buffer (udr) is ready to receive new data. if udre is one, the buffer is empty, and therefore ready to be wr itten. the udre flag ca n generate a data register empty interrupt (see description of the udrie bit). udre is set after a reset to indica te that the transmitter is ready. this bit is available in both usart and eusart modes. ? bit 4 ? fe: frame error this bit is set if the next character in the receive buff er had a frame error when receiv ed. i.e., when the first stop bit of the next character in the receive buffer is zero. this bit is valid until the receive buffer (udr) is read. the fe bit is zero when the stop bit of received data is o ne. always set this bit to zero when writing to ucsra. this bit is also valid in eusart mode only when data bits are level encoded (in manchester mode the fem bit allows to detect a framing error). ? bit 3 ? dor: data overrun this bit is set if a data overrun condition is detected. a data overrun occurs when th e receive buffer is full (two characters), it is a new character wait ing in the receive shift register, and a new start bit is detected. this bit is valid until the receive buffer (udr) is read. always set this bit to zero when writing to ucsra. this bit is available in both usart and eusart modes. ? bit 2 ? upe: usart parity error this bit is set if the next character in the receive buf fer had a parity error when received and the pa rity checking was enabled at that point (upm1 = 1). this bit is valid unt il the receive buffer (udr) is read. always set this bit to zero when writing to ucsra. this bit is also valid in eusart mode only when data bi ts are level encoded (there is no parity in manchester mode). ? bit 1 ? u2x: double the usart transmission speed this bit only has effect for the asynchronous operation. write this bit to zero when using synchronous operation. writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication. this bit is available in both usart and eusart modes. ? bit 0 ? mpcm: multi-processor communication mode this bit enables the multi-processor communication mode. when the mpcm bit is written to one, all the incoming frames received by the usart receiver that do not cont ain address informat ion will be ignored. the transmitter is unaffected by the mpcm setting. for more detailed information see ?multi-processor communication mode? on page 190 . this mode is unavailable when the eusart mode is set. 193 at90pwm216/316 [datasheet] 7710h?avr?07/2013 17.10.3 usart control and status register b ? ucsrb ? bit 7 ? rxcie: rx complete interrupt enable writing this bit to one enables interrupt on the rxc flag. a usart receive complete interrupt will be generated only if the rxcie bit is written to one, the global inte rrupt flag in sreg is written to one and the rxc bit in ucsra is set. this bit is available for both usart and eusart modes. ? bit 6 ? txcie: tx complete interrupt enable writing this bit to one enables interr upt on the txc flag. a usart transmit complete interrupt will be generated only if the txcie bit is written to one, the global interrupt flag in sreg is written to one and the txc bit in ucsra is set. this bit is available for both usart and eusart mode. ? bit 5 ? udrie: usart data re gister empty interrupt enable writing this bit to one enable s interrupt on the udre flag . a data register empty inte rrupt will be generated only if the udrie bit is written to one, the global interrupt flag in sreg is written to one and the udre bit in ucsra is set. this bit is available for both usart and eusart mode. ? bit 4 ? rxen: receiver enable writing this bit to one enables the usart receiver. the receiver will override normal port operation for the rxd pin when enabled. disabling the receiver will flush the re ceive buffer invalidating the fe, dor, and upe flags. this bit is available for both usart and eusart mode. ? bit 3 ? txen: transmitter enable writing this bit to one enables the u sart transmitter. the transmitter will override normal port operation for the txdn pin when enabled. the disabling of the transmitt er (writing txen to zero) will not become effective until ongoing and pending transmissions are completed, i.e., when the transmit shift register and transmit buffer reg- ister do not contain data to be transm itted. when disabled, the tr ansmitter will no longer override the txdn port. this bit is available for both usart and eusart mode. ? bit 2 ? ucsz2: character size the ucsz2 bits combined with the ucsz1:0 bit in ucsrc sets the number of data bits (character size) in a frame the receiver and transmitter use. this bit have no effect when the eusart mode is enabled. ? bit 1 ? rxb8: receive data bit 8 rxb8 is the ninth data bit of the received character when operating with serial frames with nine data bits. must be read before reading the low bits from udr. when the eusart mode is enable and configured in 17 bi ts receive mode, this bit contains the seventeenth bit (see eusart section). bit 76543210 rxcie txcie udrie rxen txen ucsz2 rxb8 txb8 ucsrb read/write r/w r/w r/w r/w r/w r/w r r/w initial value 00000000 194 at90pwm216/316 [datasheet] 7710h?avr?07/2013 ? bit 0 ? txb8: transmit data bit 8 txb8 is the ninth data bit in the char acter to be transmitted when operating wit h serial frames with nine data bits. must be written before wr iting the low bits to udr. when the eusart mode is enable and configured in 17 bits transmit mode, this bit contains the seventeenth bit (see eusart section). 17.10.4 usart control and status register c ? ucsrc ? bit 7 ? reserved bit this bit is reserved for future use. for compatibilty with future devices, th is bit must be written to zero when uscrc is written. ? bit 6 ? umsel: usart mode select this bit selects between asynchronous and synchronous mode of operation. when configured in eusart mode, the synchronous mode should not be set with manchester mode (see eusart section). ? bit 5:4 ? upm1:0: parity mode these bits enable and set type of parity generation and check. if enabl ed, the transmitter will automatically gener- ate and send the parity of the transmit ted data bits within each frame. the receiver will ge nerate a parity value for the incoming data and compare it to the upm setting. if a mismatch is dete cted, the upe flag in ucsra will be set. this setting is available in eusart mo de only when data bits are level encoded (in manchester the parity checker and generator are not available). ? bit 3 ? usbs: stop bit select this bit selects the number of stop bi ts to be inserted by th e transmitter. the receiv er ignores this setting. bit 76543210 - umsel0 upm1 upm0 usbs ucsz1 ucsz0 ucpol ucsrc read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000110 table 17-4. umsel bit settings umsel mode 0 asynchronous operation 1 synchronous operation table 17-5. upm bits settings upm1 upm0 parity mode 0 0 disabled 01reserved 1 0 enabled, even parity 1 1 enabled, odd parity 195 at90pwm216/316 [datasheet] 7710h?avr?07/2013 in eusart mode, the usbs bit has the same beh avior and the eusb bit of the eu sart allows to configure the number of stop bit for the receiver in this mode. ? bit 2:1 ? ucsz1:0: character size the ucsz1:0 bits combined with the ucsz2 bit in ucsrb sets the number of data bits (character size) in a frame the receiver and transmitter use. when the eusart mode is set, these bits have no effect. ? bit 0 ? ucpol: clock polarity this bit is used for synchronous mode onl y. write this bit to zero when asyn chronous mode is used. the ucpol bit sets the relationship between data output change and data inpu t sample, and the synchronous clock (xck). 17.10.5 usart baud rate registers ? ubrrl and ubrrh table 17-6. usbs bit settings usbs stop bit(s) 01-bit 12-bit table 17-7. ucsz bits settings ucsz2 ucsz1 ucsz0 character size 0005-bit 0016-bit 0107-bit 0118-bit 100reserved 101reserved 110reserved 1119-bit table 17-8. ucpol bit settings ucpol transmitted data changed (output of txdn pin) received data sampled (input on rxd pin) 0 rising xck edge falling xck edge 1 falling xck edge rising xck edge bit 151413121110 9 8 ???? ubrr[11:8] ubrrh ubrr[7:0] ubrrl 76543210 read/write rrrrr/wr/wr/wr/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 00000000 196 at90pwm216/316 [datasheet] 7710h?avr?07/2013 ? bit 15:12 ? reserved bits these bits are reserved for future use. for compatibility wit h future devices, these bit must be written to zero when ubrrh is written. ? bit 11:0 ? ubrr11:0: usart baud rate register this is a 12-bit register which contains the usart baud ra te. the ubrrh contains the fo ur most significant bits, and the ubrrl contains the eight least significant bits of the usart baud rate. ongoing transmissions by the transmitter and receiver will be co rrupted if the baud rate is changed. writing ubrrl will trigger an immediate update of the baud rate prescaler. 17.11 examples of ba ud rate setting for standard crystal, resonator and ex ternal oscillator frequencie s, the most commonly us ed baud rates for asyn- chronous operation can be generated by using the ubrr settings in table 17-9 up to table 17-12 . ubrr values which yield an actual baud rate differing less than 0.5% fr om the target baud rate, are bold in the table. higher error ratings are acceptable, but th e receiver will have less noise resistance when the error rating s are high, especially for large serial frames (see ?asynchronous operational range? on page 188 ). the error values are calculated using the following equation: error[%] 1 baudrate closest match baudrate -------------------------------------------------------- ? ?? ?? 100% ? = table 17-9. examples of ubrr settings for commonly frequencies baud rate (bps) f clk io = 1.0000 mhz f clk io = 1.8432 mhz f clk io = 2.0000 mhz u2x = 0 u2x = 1 u2x = 0 u2x = 1 u2x = 0 u2x = 1 ubrr error ubrr error ubrr error u brr error ubrr error ubrr error 2400 25 0.2% 51 0.2% 47 0.0% 95 0.0% 51 0.2% 103 0.2% 4800 12 0.2% 25 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2% 9600 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2% 14.4k 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 19.2k 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 28.8k 1 8.5% 3 8.5% 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 38.4k 1 -18.6% 2 8.5% 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 57.6k 0 8.5% 1 8.5% 1 0.0% 3 0.0% 1 8.5% 3 8.5% 76.8k ? ? 1 -18.6% 1 -25.0% 2 0.0% 1 -18.6% 2 8.5% 115.2k ? ? 0 8.5% 0 0.0% 1 0.0% 0 8.5% 1 8.5% 230.4k??????00.0%???? 250k???????????? 500k???????????? 1m ???????????? max. (1) 62.5 kbps 125 kbps 115.2 kbps 230.4 kbps 125 kpbs 250 kbps 1. ubrr = 0, error = 0.0% 197 at90pwm216/316 [datasheet] 7710h?avr?07/2013 table 17-10. examples of ubrr settings for commonly frequencies (continued) baud rate (bps) f clk io = 3.6864 mhz f clk io = 4.0000 mhz f clk io = 7.3728 mhz u2x = 0u2x = 1u2x = 0u2x = 1u2x = 0u2x = 1 ubrr error ubrr error ubrr error u brr error ubrr error ubrr error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0% 19.2k 11 0.0% 23 0.0% 12 0. 2% 25 0.2% 23 0.0% 47 0.0% 28.8k 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 15 0.0% 31 0.0% 38.4k 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 57.6k 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 76.8k 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 115.2k 1 0.0% 3 0.0% 1 8.5% 3 8.5% 3 0.0% 7 0.0% 230.4k 0 0.0% 1 0.0% 0 8.5% 1 8.5% 1 0.0% 3 0.0% 250k 0 -7.8% 1 -7.8% 0 0.0% 1 0.0% 1 -7.8% 3 -7.8% 500k ? ? 0 -7.8% ? ? 0 0.0% 0 -7.8% 1 -7.8% 1m ??????????0-7.8% max. (1) 230.4 kbps 460.8 kbps 250 kbps 0.5 mbps 460.8 kpbs 921.6 kbps 1. ubrr = 0, error = 0.0% 198 at90pwm216/316 [datasheet] 7710h?avr?07/2013 table 17-11. examples of ubrr settings for commonly frequencies (continued) baud rate (bps) f clk io = 8.0000 mhz f clk io = 10.000 mhz f clk io = 11.0592 mhz u2x = 0 u2x = 1 u2x = 0 u2x = 1 u2x = 0 u2x = 1 ubrr error ubrr error ubrr error u brr error ubrr error ubrr error 2400 207 0.2% 416 -0.1% 259 0.2% 520 0.0% 287 0.0% 575 0.0% 4800 103 0.2% 207 0.2% 129 0.2% 259 0.2% 143 0.0% 287 0.0% 9600 51 0.2% 103 0.2% 64 0.2% 129 0.2% 71 0.0% 143 0.0% 14.4k 34 -0.8% 68 0.6% 42 0.9% 86 0.2% 47 0.0% 95 0.0% 19.2k 25 0.2% 51 0.2% 32 -1.4% 64 0.2% 35 0.0% 71 0.0% 28.8k 16 2.1% 34 -0.8% 21 -1.4% 42 0.9% 23 0.0% 47 0.0% 38.4k 12 0.2% 25 0.2% 15 1.8% 32 -1.4% 17 0.0% 35 0.0% 57.6k 8 -3.5% 16 2.1% 10 -1.5% 21 -1.4% 11 0.0% 23 0.0% 76.8k 6 -7.0% 12 0.2% 7 1.9% 15 1.8% 8 0.0% 17 0.0% 115.2k 3 8.5% 8 -3.5% 4 9.6% 10 -1.5% 5 0.0% 11 0.0% 230.4k 1 8.5% 3 8.5% 2 -16.8% 4 9.6% 2 0.0% 5 0.0% 250k 1 0.0% 3 0.0% 2 -33.3% 4 0.0% 2 -7.8% 5 -7.8% 500k 0 0.0% 1 0.0% ? ? 2 -33.3% ? ? 2 -7.8% 1m ??00.0%???????? max. (1) 0.5 mbps 1 mbps 625 kbps 1.25 mbps 691.2 kbps 1.3824 mbps 1. ubrr = 0, error = 0.0% 199 at90pwm216/316 [datasheet] 7710h?avr?07/2013 table 17-12. examples of ubrr settings for commonly frequencies (continued) baud rate (bps) f clk io = 12.0000 mhz f clk io = 14.7456 mhz f clk io = 16.0000 mhz u2x = 0 u2x = 1 u2x = 0 u2x = 1 u2x = 0 u2x = 1 ubrr error ubrr error ubrr error u brr error ubrr error ubrr error 2400 312 -0.2% 624 0.0% 383 0.0% 767 0.0% 416 -0.1% 832 0.0% 4800 155 0.2% 312 -0.2% 191 0.0% 383 0.0% 207 0.2% 416 -0.1% 9600 77 0.2% 155 0.2% 95 0.0% 191 0.0% 103 0.2% 207 0.2% 14.4k 51 0.2% 103 0.2% 63 0.0% 127 0.0% 68 0.6% 138 -0.1% 19.2k 38 0.2% 77 0.2% 47 0. 0% 95 0.0% 51 0.2% 103 0.2% 28.8k 25 0.2% 51 0.2% 31 0.0% 63 0.0% 34 -0.8% 68 0.6% 38.4k 19 -2.5% 38 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2% 57.6k 12 0.2% 25 0.2% 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 76.8k 9 -2.7% 19 -2.5% 11 0.0% 23 0.0% 12 0.2% 25 0.2% 115.2k 6 -8.9% 12 0.2% 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 230.4k 2 11.3% 6 -8.9% 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 250k 2 0.0% 5 0.0% 3 -7.8% 6 5.3% 3 0.0% 7 0.0% 500k ? ? 2 0.0% 1 -7.8% 3 -7.8% 1 0.0% 3 0.0% 1m ? ? ? ? 0 -7.8% 1 -7.8% 0 0.0% 1 0.0% max. (1) 750 kbps 1.5 mbps 921.6 kbps 1.8432 mbps 1 mbps 2 mbps 1. ubrr = 0, error = 0.0% 200 at90pwm216/316 [datasheet] 7710h?avr?07/2013 18. eusart (extended usart) the extended universal synchronous and asynchronous se rial receiver and transmitter (eusart) provides functionnal extensions to the usart. 18.1 features ? independant bit number configuration for transmit and receive ? supports serial frames with 5, 6, 7, 8, 9 or 13, 14, 15, 16, 17 data bits and 1 or 2 stop bits ? biphase manchester encoder/de coder (for dali communications) ? manchester framing error detection ? bit ordering (msb first or lsb first) 18.2 overview a simplified block diagram of the eusart transmitter is shown in figure 18-1 . cpu accessible i/o registers and i/o pins are shown in bold. figure 18-1. eusart block diagram the eusart is activated with the eusart bit of eucsrb re gister. until this bit is not set, the usart will behave as standard usart, all the functionnalit ies of the eusart are not accessible. parity generator ubrr[h:l] udr (transmit) eudr (transmit) udr (receive) eudr (receive) ucsra ucsrb ucsrc eucsra eucsrb eucsrc baud rate generator transmit shift register receive shift register rxd txd pin control pin control xck data recovery clock recovery pin control tx control rx control parity checker manchester encoder data bus clkio sync logic clock generator transmitter receiver manchester decoder 201 at90pwm216/316 [datasheet] 7710h?avr?07/2013 the eusart supports more serial frame fo rmats than the standard usart interface: ? asynchonous frames ? standard bit level encoded ? manchester bit encoded ? synchronous frames ? in this mode only the standard bit level encoded is available 18.3 serial frames a serial frame is defined to be one char acter of data bits with sync hronization bits (start an d stop bits), and option- ally a parity bit for error checking. 18.3.1 frame formats the eusart allows to receive and transmit serial frame with the following format: ? 1 start bit ? 5, 6, 7, 8, 9, 13, 14,15,16,17 data bits ? data bits and start bit level encoded or manchester encoded ? data transmition msb or lsb first (bit ordering) ? no, even or odd parity bit ? 1 or 2 stop bits: ? stop bits insertion for transmition ? stop bits value read access in reception the frame format used by the eusart can be configur ed through the following usart/eusart registers: ? utxs3:0 and urxs3:0 (eucsra of eusart register) select the number of data bits per frame ? upm1:0 bits enable and set the type of parity bit (wh en configured in manchester mode, the parity should be fixed to none). usbs (ucsrc register of usart) and eusbs (eucsrb register of eusart) select the number of stop bits to be processed respectively by the transmiter and the receiv er. the receiver stores the two stop bit values when con- figured in manchester mode. when configured in level encoded mode, the second stop bit is ignored (behavior similar as the usart). 18.3.2 parity bit calculation the parity bit behavior is similar to the usart mode, except for the manchester encoded mode, where no parity bit can be inserted or detected (shoul d be configured to none with the upm1:0 bits. the parity bit is calculated by doing an exclusive-or of all the data bits. if odd parity is us ed, the result of the exclusive or is inverted. the relation between the parity bit and data bits is as follows: p even parity bit using even parity p odd parity bit using odd parity d n data bit n of the character if used, the parity bit is located between the last data bit and first stop bit of a serial frame. p even d n 1 ? ? d 3 d 2 d 1 d 0 0 p odd ?????? d n 1 ? ? d 3 d 2 d 1 d 0 1 ?????? = = 202 at90pwm216/316 [datasheet] 7710h?avr?07/2013 18.3.3 manchester encoding manchester encoding (also know as biphase code) is a synchronous cl ock encoding techni que used to encode the clock and data of a synchronous bit stream. in this technique, th e actual binary data to be transmitted are not sent as a sequence of logic 1's and 0's as in level enco ded way as in standard usart (known technically as non return to zero (nrz)). instead, the bits are translated in to a slightly different format that has a number of advan- tages over using straight binary encoding (i.e. nrz). manchester encoding follows the rules: ? if the original data is a logic 1, the manchester code is: 0 to 1 (upward transition at bit center) ? if the original data is a logic 0, the manchester co de is: 1 to 0 (downward transition at bit center) figure 18-2. manchester bi-phase levels 18.3.3.1 manchester frame the usart supports manchester encoded fr ames with the followi ng characteristics: ? one start bit manchester encoded (logical ?1?) ? 5, 6, 7, 8, 9, 13, 14,15,16,17 data bits in transmission or reception (msb or lsb first) ? the number of data bit in a frame is independently configurable in reception and transmission mode. ? one or two stop bits (level encoded) figure 18-3. manchester frame example 18.3.3.2 manchester decoder when configured in manchester mode, the eusart receiver is able to receive serial frame using a 17-bit shift reg- ister, an edge detector and several data/control register s. the manchester decoder receives a frame from the rxd pin of the eusart interface and loads the received da ta in the eusart data register (udr and eudr). the bit order of the data bits in the frame is configurable to handle msb or lsb first. logical 0 logical 1 1 0 0 1 1 1 1 0 1 0 0 1 0 1 0 1 0 start bit data bits (up to 17 data bit) stop bits encoder clock manchester data binary data 203 at90pwm216/316 [datasheet] 7710h?avr?07/2013 the polarity of the bi-phase start is not configurable. the start bit a logical ?1? (rising edge at bit center). the polarity of the stop bits is not configurable, the inte rface allows to read the 2 stops bits value by software. the manchester decoder is enable when the eusart is configured in manchester mode and the rxen of uscrb set (global usart receive enable). the number of data bits to be received can be configured with the urxs bits of eucsra register. the manchester decoder provides a special mode where 16 or 17 data bits can be received. in this mode the man- chester decoder can automatical ly detects if the seventee nth bit is manchester encode d or not (seventeenth data bit or first stop bit). if the receiver detects a valid data bit (manchester transition) duri ng the seventeenth bit time of the frame, the receiver will process the frame as a 17-bit frame lenght and se t the f1617 bit of eucsrc register. in manchester mode, the clock used for sampling the eusart input signal is programmed by the baudrate generator. the edge detector of the manchester decoder is based upon a 16 bits up/down counter which maximum value can be configured through the mubrrh and mubrrl registers. the maximum counter value is given by the following formula: mubrr[h:l]=f clkio / (baud rate frequency) mburr[h:l] is used to calibrate the detect window of the start bit and to detect time overflow of the other bits. 18.3.4 double speed operation (u2x) double speed operation is cont rolled by u2x bit in ucsra. see ?double speed operation (u2x)? on page 176. this mode of operation is not allowed in manchester bit coding. each ?bit time? in the manchester serial frame is divided into two phases (see figure 18-4 ). the counter counts dur- ing the first phase and counts down during the second one. when the data bit transition is detected, the counter memorises the n1 counter value and start counting down. when the counter reaches the zero value, it starts counting up again and the n1/2 value allows to open the next detection window. this detection window defines the time zone where the next data bit edge is sampled. figure 18-4. manchester decoder operation note: n1 = mburr[h:l]/2 204 at90pwm216/316 [datasheet] 7710h?avr?07/2013 18.3.4.1 manchester fr aming error detection when configured in manchester mode, the framing error (f e) of the uscra register is not used, the eusart gen- erates a dedicated frame error manchester (fem) when a data data bit is not detected during the detection window (see figure 18-5 ). n2 n1 n3 manchester data manchester decoder counter internal manchester clock n1/2 n2/2 data clock bit 1 bit 2 start bit start bit decoded data detection window n3/2 n4 bit 3 delayed edge n2/4 n3/4 n4/4 205 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 18-5. manchester frame error detection note: counter overflow = mburr[h:l] when a manchester framing error is detected the fem bit and rxc bit are set at the same time. this allows the application to execute the reception complete interrupt subroute when this erro r condition is detected. when a manchester framing error is detected, the eusart receiver immediately enters in a new start bit detection phase. thus when a manchester framing er ror is detected within a frame, the re ceiver will process the rest of the frame as a new incoming frame and generate other fem errors. internal manchester clock start bit n2 n1 bit 1 start bit bit 2 back shift start bit n2 n1 bit 1 start bit front shift bit 2 n3 framing error manchester data manchester decoder counter internal manchester clock edge detection space n1/2 resynchronize internal manchester clock n2/4 n3 n2/2 counter overflow transition outside the detect window the counter reaches the counter overflow value without reaching a manchester edge 206 at90pwm216/316 [datasheet] 7710h?avr?07/2013 18.4 configuring the eusart 18.4.1 data transmission ? eusart transmitter the eusart transmitter is enabled in the same way as standard usart, by setting the transmit enable (txen) bit in the ucsrb register. when the tr ansmitter is enabled, the normal port operation of the txdn pin is overrid- den by the eusart and given the functi on as the transmitter?s serial outpu t. the baud rate, mode of operation and frame format must be set up once before doing any tran smissions. if synchronous operation is used, the clock on the xck pin will be overridden and used as transmission clock. 18.4.2 sending frames with 5 to 8 data bit in this mode the behavior is the same as the standar d usart (see ?sending frames with 5 to 8 data bit? in usart section). 18.4.3 sending frames with 9, 13, 14, 15 or 16 data bit in these configurations the most significant bits (9, 13, 14, 15 or 16) should be loaded in the eudr register before the low byte of the character is written to udr. the write operation in the udr register allows to start the transmission. note: the example code assumes that the part specific header file is included. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructions t hat allow access to extended i/o. typically ?lds? and ?sts? combined with ?sbrs?, ?sbrc?, ?sbr?, and ?cbr?. 18.4.4 sending 17 data bit frames in this configuration the seventeenth bit shoud be loaded in the rxb8 bit register, the rest of the most significant bits (9, 10, 11, 12, 13, 14, 15 and 16) should be loaded in the eudr register, before the low byte of the character is written to udr. assembly code example (1) eusart_transmit: ; wait for empty transmit buffer sbis ucsra,udre rjmp eusart_transmit ; put lsb data (r16) and msn data (r15) into buffer, sends the data sts eudr,r15 sts udr,r16 ret c code example (1) void eusart_transmit( unsigned int data ) { /* wait for empty transmit buffer */ while ( !( ucsra & (1< 207 at90pwm216/316 [datasheet] 7710h?avr?07/2013 18.4.5 transmitter flags and interrupts the behavior of the eusart is the same as in usart mode (see ?receive complete flag and interrupt?). the interrupts generation and handling for transmissi on in eusart mode are the same as in usart mode. 18.4.6 disabling the transmitter the disabling of the transmitter (setting the txen to zero) will not become effective until ongoing and pending transmissions are completed, i.e., when the transmit shif t register and transmit buffer register do not contain data to be transmitted. 18.4.7 data reception ? eusart receiver 18.5 data reception ? eusart receiver the eusart receiver is enabled by writing the receive enable (rxen) bit in the ucsrb register to one (same as usart). when the receiver is enabled, the normal pi n operation of the rxd pin is overridden by the eusart and given the function as the receiver?s serial input. the baud rate, mode of operation and frame format must be set up once before any serial reception can be done. if synchronous operation is used, the clock on the xck pin will be used as transfer clock. 18.5.1 receiving frames with 5 to 8 data bits in this mode the behavior is the same as the standard us art (see ?receiving frames with 5 to 8 data bits? in usart section). 18.5.2 receiving frames with 9, 13, 14, 15 or 16 data bits in these configurations the most signi ficant bits (9, 13, 14, 15 or 16) should be read in the eudr register before reading the of the character in the udr register. read status from eucsrc, then data from udr. the following code example shows a simple eusart receive function. 208 at90pwm216/316 [datasheet] 7710h?avr?07/2013 note: the example code assumes that the part specific header file is included. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructions t hat allow access to extended i/o. typically ?lds? and ?sts? combined with ?sbrs?, ?sbrc?, ?sbr?, and ?cbr?. 18.5.3 receiving 17 data bit frames in this configuration the seventeenth bit shoud be read from the rxb8 bit register, the rest of the most significant bits (9, 10, 11, 12, 13, 14, 15 and 16) should be read from the eudr register, before the low byte of the character is read from udr. 18.5.4 receive complete flag and interrupt the eusart receiver has the same usart flag that indicates the receiver state. see ?receive complete flag and interrupt? in usart section. 18.5.5 receiver error flags when the eusart is not conf igured in manchester mode, the eusart ha s the three same errors flags as stan- dard mode: frame error (fe), data overrun (dor) and parity error (upe). all can be accessed by reading ucsra. (see ?receiver error flags? in usart section). when the eusart is configured in machester mode, the eusart has two errors flags: data overrun (dor), and manchester framing error (fem bit of eucsrc). all the receiver error flags are valid only when the rxc bit is set and until the udr register is read. assembly code example (1) eusart_receive: ; wait for data to be received sbis ucsra, rxc rjmp eusart_receive ; get msb (r15), lsb (r16) lds r15, eudr lds r16, udr ret c code example (1) unsigned int eusart_receive( void ) { unsigneg int rx_data /* wait for data to be received */ while ( !(ucsra & (1< 210 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 18-6. 9 bits communication data access 18.6.2.3 udr/eudr data access from 13 to 17 bits per character when the eusart is used in 13, 14, 15, 16 or 17 bits per character mode, the eudr /udr registers are used in combination with the rxb8/txb8 bit for data access. for 13, 14, 15 or 16 bit character the upper unused bits in eudr will be ignored by the transmitter and set to zero by the receiver. in transmitte r mode, the data should be written msb firs t. the data transmis sion starts when the udr register is written. in these modes, the rxb8/txb 8 registers are not used. figure 18-7. 13, 14, 15 and 16 bits communication data access for 17 bit character the seventeenth bit is locate in rxb8 or txb8 register. in transmit ter mode, the data should be written msb first. the data transmission st arts when the udr re gister is written. figure 18-8. 17 bits communication data access 87 0 data 8:0 udr eudr 8 15 7 0 data 15:0 udr eudr 8 15 16 7 0 data 16:0 udr eudr rxb8 (receive) or txb8 (transmit) 211 at90pwm216/316 [datasheet] 7710h?avr?07/2013 18.6.3 eusart control and st atus register a ? eucsra ? bit 7:4 ? eusart transmit character size the utxs3:0 bits sets the number of data bits (character size) in a frame the transmitter use. ? bit 3:0 ? eusart receive character size the utxs3:0 bits sets the number of data bits (character size) in a frame the receiver use. bit 76543210 utxs3 utxs2 utxs1 utxs0 urxs3 urxs2 urxs1 urxs0 eucsra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 00110011 table 18-1. utxs bits settings utxs3 utxs2 utxs1 utxs0 transmit character size 00005-bit 00016-bit 00107-bit 00118-bit 0100reserved 0101reserved 0110reserved 01119-bit 100013-bit 100114-bit 101015-bit 101116-bit 1100reserved 1101reserved 1110reserved 111117-bit table 18-2. urxs bits settings urxs3 urxs2 urxs1 urxs0 receive character size 00005-bit 00016-bit 00107-bit 00118-bit 0100reserved 0101reserved 0110reserved 01119-bit 100013-bit 100114-bit 212 at90pwm216/316 [datasheet] 7710h?avr?07/2013 18.6.4 eusart control register b ? eucsrb ? bit 7:5 ?reserved bits these bits are reserved for future use. for compatibility wi th future devices, these bits must be written to zero when euscrb is written. ? bit 4 ? eusart enable bit set to enable the eusart mode, clear to operate as standard usart. ? bit 3? eusbs enable bit this bit selects the number of stop bits detected by the receiver. note: the number of stop bit inserted by the transmitter in eusart mode is configur able through the usbs bit of in the of the usart. ? bit 2?reserved bit this bit is reserved for future use. for compatibility with future devices, this bit must be written to zero when euscrb is written. ? bit 1 ? manchester mode when set the eusart operates in manchester encod er/decoder mode (manchester encoded frames). when cleared the eusart detected and transmit level encoded frames. 101015-bit 101116-bit 1100reserved 1101reserved 1110 16 or 17 bit (for manchester encoded only mode) 111117-bit table 18-2. urxs bits settings urxs3 urxs2 urxs1 urxs0 receive character size bit 76543210 - - - eusart eusbs - emch bodr eucsrb read/write r r r r/w r/w r r/w r/w initial value 00000000 table 18-3. eusbs bit settings eusbs receiver stop bit(s) 01-bit 12-bit 213 at90pwm216/316 [datasheet] 7710h?avr?07/2013 as in manchester mode the parity checker and generator are unavailable, the parity should be configured to none ( write upm1:0 to 00 in ucsrc), see table 17-5. ? bit 0 ?bit order this bit allows to change the bit ordering in the transmit and received frames. clear to transmit and receive lsb first (standard usart mode) set to transmit and receive msb first. 18.6.5 eusart status register c ? eucsrc ? bit 7:4 ?reserved bits these bits are reserved for future use. for compatibility wi th future devices, these bits must be written to zero when euscrc is written. ? bit 3 ?frame error manchester this bit is set by hardware when a framing error is detect ed in manchester mode. this bit is valid when the rxc bit is set and until the receive buffer (udr) is read. ? bit 2 ?f1617 when the receiver is configured for 16 or 17 bits in m anchester encoded mode, this bit indicates if the received frame is 16 or 17 bits length. cleared: indicates that the receiv ed frame is 16 bits length. set: indicates that th e received frame is 17 bits length. this bit is valid when the rxc bit is se t and until the receive buffer (udr) is read. ? bit 1:0 ?stop bits values when manchester mode is activated, these bits contains the stop bits value of the previous received frame. when the data bits in the serial frame are stan dard level encoded, these bits are not updated. table 18-4. usart/eusart modes selection summary umsel emch eusart mode 0x0 asynchronous up to 9 bits level encoded (standard asynchronous usart mode) 1x0 synchronous up to 9 bits level encoded (standard synchronous usart mode) 0 0 1 asynchronous up to 17 bits level encoded 0 1 1 asynchronous up to 17 bits manchester encoded 1 0 1 synchronous up to 17 bits level encoded 111reserved bit 76543210 ----femf1617stp1stp0eucsrc read/write rrrrrrrr initial value 00000000 214 at90pwm216/316 [datasheet] 7710h?avr?07/2013 18.6.6 manchester receiver baud rate registers ? mubrrl and mubrrh ? bit 15:0 ? mubrr15:0: manchester receiver baud rate register this is a 16-bit register which contains the maximum value for the manchester receiver counter. the mubrrh contains the eight most significant bits, and the mubrrl contains the eight least significant bits. ongoing trans- missions by the receiver will be corr upted if the baud rate is changed. mubrr[h:l]=f clkio / (baud rate frequency) bit 151413121110 9 8 mubrr[15:8] mubrrh mubrr[7:0] mubrrl 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 00000000 table 18-5. examples of mubrr settings for commonly frequencies baud rate (bps) f clk io = 1 mhz f clk io = 1.8432 mhz f clk io = 2.0000 mhz f clk io = 4.0000 mhz f clk io = 8.0000 mhz f clk io = 11.0592 mhz f clk io = 16.000 mhz 1200 833 1536 1667 3333 6667 9216 13333 2400 417 768 833 1667 3333 4608 6667 4800 208 384 417 833 1667 2304 3333 9600 104 192 208 417 833 1152 1667 215 at90pwm216/316 [datasheet] 7710h?avr?07/2013 19. analog comparator the analog comparator compares the input values on the positive pin acmp x and negative pin acmpm. 19.1 overview the at90pwm216/316 features three fast analog comparators. each comparator has a dedicated input on the positive input, and the negative input can be configured as: ? a steady value among the 4 internal reference levels defi ned by the vref selected thanks to the refs1:0 bits in admux register. ? a value generated from the internal dac ? an external analog input acmpm. when the voltage on the positive acmpn pin is higher than the voltage selected by the acnm multiplexer on the negative input, the analog comparator output, acno, is set. the comparator is a clocked co mparator. a new comparison is done on the falling edge of clk i/o . each comparator can trigger a separate interrupt, exclus ive to the analog comparator. in addition, the user can select interrupt triggering on comparator output rise, fall or toggle. the interrupt flags can also be used to synchronize adc or dac conversions. moreover, the comparator?s output of the comparator 1 can be set to trigger the ti mer/counter1 input capture function. the comparator as no hysteresis on the rising edge (0 > 1) and a half -hysteresis on the falling edge (1 -> 0). a block diagram of the three comparators and their surrounding logic is shown in figure 19-1 . 216 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 19-1. analog comparator block diagram (1)(2) notes: 1. adc multiplexer output: see table 20-4 on page 235 . 2. refer to figure 2-1 on page 2 and for analog comparator pin placement. 3. the voltage on vref is defined in 20-3 ?adc voltage reference selection? on page 235 19.2 analog comparator register description each analog comparator has its own control register. a dedicated register has been designed to consign the outputs and the flags of the 3 analog comparators. 19.2.1 analog comparator 0 control register ? ac0con ? bit 7? ac0en: analog comparator 0 enable bit set this bit to enable the analog comparator 0. clear this bit to disable the analog comparator 0. ? bit 6? ac0ie: analog comparator 0 interrupt enable bit set this bit to enable the analog comparator 0 interrupt. clear this bit to disable the analog comparator 0 interrupt. + - interrupt sensitivity control analog comparator 0 interrupt ac0ie ac0if ac0o ac0is1 ac0is0 + - interrupt sensitivity control analog comparator 1 interrupt ac1ie t1 capture trigger ac1ice ac1if ac1o ac1is1 ac1is0 + - interrupt sensitivity control analog comparator 2 interrupt ac0ie ac2if ac2o ac2is1 ac2is0 acmp0 acmp1 acmp2 ac2en /3.20 /2.13 /1.60 /6.40 acmpm vref dac ac0m 2 1 0 dac result ac1en ac0en ac1m 2 1 0 ac2m 2 1 0 internal 2.56v reference refs0 refs1 aref avcc dacen clk i/o clk i/o clk i/o (/2) (/2) (/2) bit 76543210 ac0en ac0ie ac0is1 ac0is0 - ac0m2 ac0m1 ac0m0 ac0con read/write r/w r/w r/w r/w - r/w r/w r/w initial value 0 0 0 0 0 0 0 0 217 at90pwm216/316 [datasheet] 7710h?avr?07/2013 ? bit 5, 4? ac0is1, ac0is0: analog comparator 0 interrupt select bit these 2 bits determine the sensitivity of the interrupt trigger. the different setting are shown in table 19-1 . ? bit 2, 1, 0? ac0m2, ac0m1, ac0m0: analog comparator 0 multiplexer register these 3 bits determine the input of the negative input of the analog comparator. the different setting are shown in table 19-2 . 19.2.2 analog comparator 1control register ? ac1con ? bit 7? ac1en: analog comparator 1 enable bit set this bit to enable the analog comparator 1. clear this bit to disable the analog comparator 1. ? bit 6? ac1ie: analog comparator 1 interrupt enable bit set this bit to enable the analog comparator 1 interrupt. clear this bit to disable the analog comparator 1 interrupt. ? bit 5, 4? ac1is1, ac1is0: analog comparator 1 interrupt select bit these 2 bits determine the sensitivity of the interrupt trigger. the different setting are shown in table 19-1 . table 19-1. interrupt sensit ivity selection ac0is1 ac0is0 description 0 0 comparator interrupt on output toggle 01reserved 1 0 comparator interrupt on output falling edge 1 1 comparator interrupt on output rising edge table 19-2. analog comparator 0 negative input selection ac0m2 ac0m1 ac0m0 description 0 0 0 ?vref?/6.40 0 0 1 ?vref?/3.20 0 1 0 ?vref?/2.13 0 1 1 ?vref?/1.60 1 0 0 analog comparator negative input (acmpm pin) 1 0 1 dac result 110reserved 111reserved bit 76543210 ac1en ac1ie ac1is1 ac1is0 ac1ice ac1m2 ac1m1 ac1m0 ac1con read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 218 at90pwm216/316 [datasheet] 7710h?avr?07/2013 ? bit 3? ac1ice: analog comparator 1 interrupt capture enable bit set this bit to enable the input capture of the timer/coun ter1 on the analog comparator event. the comparator out- put is in this case directly connected to the input capture fron t-end logic, making the co mparator utilize the noise canceler and edge select featur es of the timer/counter1 input capture in terrupt. to make the comparator trigger the timer/counter1 input capture interrupt, the icie1 bit in the timer interrupt mask register (timsk1) must be set. in case ices1 bit ( ?timer/counter1 cont rol register b ? tccr1b? on page 117 ) is set high, the rising edge of ac1o is the capture/trigger event of th e timer/counter1, in case ices1 is set to zero, it is the falling edge which is taken into account. clear this bit to disable this function. in this ca se, no connection between the analog comparator and the input capture function exists. ? bit 2, 1, 0? ac1m2, ac1m1, ac1m0: analog comparator 1 multiplexer register these 3 bits determine the input of the negative input of the analog comparator. the different setting are shown in table 19-4 . 19.2.3 analog comparator 2 control register ? ac2con ? bit 7? ac2en: analog comparator 2 enable bit set this bit to enable the analog comparator 2. clear this bit to disable the analog comparator 2. table 19-3. interrupt sensit ivity selection ac1is1 ac1is0 description 0 0 comparator interrupt on output toggle 01reserved 1 0 comparator interrupt on output falling edge 1 1 comparator interrupt on output rising edge table 19-4. analog comparator 1 negative input selection ac1m2 ac1m1 ac1m0 description 0 0 0 ?vref?/6.40 0 0 1 ?vref?/3.20 0 1 0 ?vref?/2.13 0 1 1 ?vref?/1.60 1 0 0 analog comparator negative input (acmpm pin) 1 0 1 dac result 110reserved 111reserved bit 76543210 ac2en ac2ie ac2is1 ac2is0 ac2m2 ac2m1 ac2m0 ac2con read/write r/w r/w r/w r/w - r/w r/w r/w initial value 0 0 0 0 0 0 0 0 219 at90pwm216/316 [datasheet] 7710h?avr?07/2013 ? bit 6? ac2ie: analog comparator 2 interrupt enable bit set this bit to enable the analog comparator 2 interrupt. clear this bit to disable the analog comparator 2 interrupt. ? bit 5, 4? ac2is1, ac2is0: analog comparator 2 interrupt select bit these 2 bits determine the sensitivity of the interrupt trigger. the different setting are shown in table 19-1 . ? bit 2, 1, 0? ac2m2, ac2m1, ac2m0: analog comparator 2 multiplexer register these 3 bits determine the input of the negative input of the analog comparator. the different setting are shown in table 19-6 . 19.2.4 analog comparator status register ? acsr ? bit 6? ac2if: analog comparator 2 interrupt flag bit this bit is set by hardware when comparator 2 output ev ent triggers off the interrupt mode defined by ac2is1 and ac2is0 bits in ac2con register. this bit is cleared by hardware when the corresponding interrupt vector is executed in case the ac2ie in ac2con register is set. anyway, this bit is cleared by writing a logical one on it. this bit can also be used to synchronize adc or dac conversions. ? bit 5? ac1if: analog comparator 1 interrupt flag bit this bit is set by hardware when comparator 1 output ev ent triggers off the interrupt mode defined by ac1is1 and ac1is0 bits in ac1con register. this bit is cleared by hardware when the corresponding interrupt vector is executed in case the ac1ie in ac1con table 19-5. interrupt sensit ivity selection ac2is1 ac2is0 description 0 0 comparator interrupt on output toggle 01reserved 1 0 comparator interrupt on output falling edge 1 1 comparator interrupt on output rising edge table 19-6. analog comparator 2 negative input selection ac2m2 ac2m1 ac2m0 description 0 0 0 ?vref?/6.40 0 0 1 ?vref?/3.20 0 1 0 ?vref?/2.13 0 1 1 ?vref?/1.60 1 0 0 analog comparator negative input (acmpm pin) 1 0 1 dac result 110reserved 111reserved bit 76543210 ? ac2if ac1if ac0if clkpll ac2o ac1o ac0o acsr read/write - r/w r/w r/w - r r r initial value 0 0 0 0 0 0 0 0 220 at90pwm216/316 [datasheet] 7710h?avr?07/2013 register is set. anyway, this bit is cleared by writing a logical one on it. this bit can also be used to synchronize adc or dac conversions. ? bit 4? ac0if: analog comparator 0 interrupt flag bit this bit is set by hardware when comparator 0 output ev ent triggers off the interrupt mode defined by ac0is1 and ac0is0 bits in ac0con register. this bit is cleared by hardware when the corresponding interrupt vector is executed in case the ac0ie in ac0con register is set. anyway, this bit is cleared by writing a logical one on it. this bit can also be used to synchronize adc or dac conversions. ? bit 3? clkpll: pll output clock selection set this bit to select th e 8mhz or the 16mhz i/o clock from the 32/64 mhz pll as clock for analog comparator: 8 mhz if pll=32mhz 16mhz if pll=64mhz if cksel fuse is already set, a read of this bit will confirm that pll/4 clock is the source of the clock. clear this bit to select the clk i/o standard clock. ? bit 2? ac2o: analog comparator 2 output bit ac2o bit is directly the outpu t of the analog comparator 2. set when the output of the comparator is high. cleared when the output comparator is low. ? bit 1? ac1o: analog comparator 1 output bit ac1o bit is directly the outpu t of the analog comparator 1. set when the output of the comparator is high. cleared when the output comparator is low. ? bit 0? ac0o: analog comparator 0 output bit ac0o bit is directly the outpu t of the analog comparator 0. set when the output of the comparator is high. cleared when the output comparator is low. 19.2.5 digital input disa ble register 0 ? didr0 ? bit 3:2 ? acmpm and acmp2d: acmp m and acmp2 digital input disable when this bit is written logic one, the digital input bu ffer on the corresponding analog pin is disabled. the corre- sponding pin register bit will always read as zero when this bit is set. when an analog signal is applied to one of these pins and the digital input from this pin is not needed , this bit should be written logic one to reduce power con- sumption in the di gital input buffer. bit 76543210 adc7d adc6d adc5d adc4d adc3d acmpm adc2d acmp2d adc1d adc0d didr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 221 at90pwm216/316 [datasheet] 7710h?avr?07/2013 19.2.6 digital input disa ble register 1? didr1 ? bit 5, 2: acmp0d and ac mp1 digital input disable when this bit is written logic one, th e digital input buffer on the correspondi ng analog pin is disabled. the corre- sponding pin register bit will always read as zero when this bit is set. when an analog signal is applied to one of these pins and the digital input from this pin is not needed , this bit should be written logic one to reduce power con- sumption in the di gital input buffer. bit 76543210 - - acmp0d amp0pd amp0nd adc10d acmp1d adc9d amp1pd adc8d amp1nd didr1 read/write - - r/w r/w r/w r/w r/w r/w initial value 00000000 222 at90pwm216/316 [datasheet] 7710h?avr?07/2013 20. analog to digital converter - adc 20.1 features ? 10-bit resolution ? 0.5 lsb integral non-linearity ? 2 lsb absolute accuracy ? 8- 320 s conversion time ? up to 125 ksps at maximum resolution ? 11 multiplexed single ended input channels ? two differential input channels with accurate programmable gain 5, 10, 20 and 40 ? optional left adjustment for adc result readout ? 0 - v cc adc input voltage range ? selectable 2.56 v adc reference voltage ? free running or single conversion mode ? adc start conversion by auto triggering on interrupt sources ? interrupt on adc conversion complete ? sleep mode noise canceler the at90pwm216/316 features a 10-bit successive approx imation adc. the adc is connected to an 15-channel analog multiplexer which allows eleven single-ended input. the single-ended voltage inputs refer to 0v (gnd). the device also supports 2 differential voltage input combinations which are equipped with a programmable gain stage, providing amplification steps of 14db (5x), 20 db (10x ), 26 db (20x), or 32db (4 0x) on the differential input voltage before the a/d conversion. on the amplif ied channels, 8-bit resolution can be expected. the adc contains a sample and hold circuit which ensures that the input voltage to the adc is held at a constant level during conversion. a block diagram of the adc is shown in figure 20-1 . the adc has a separate analog supply voltage pin, av cc . av cc must not differ more than 0.3v from v cc . see the paragraph ?adc noise canceler? on page 228 on how to connect this pin. internal reference voltages of nominally 2.56v or av cc are provided on-chip. the voltage reference may be exter- nally decoupled at the aref pin by a capacitor for better noise performance. 223 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 20-1. analog to digital converter block schematic mux2 mux1 mux0 mux3 refs1 refs0 adlar - adps2 adps1 adps0 adie aden adsc adate adif admux adcsra adts2 adts1 adts0 --- adcsrb edge detector sources adc0 adc1 adc2 adc3 adc4 adc5 adc6 adc7 amp1-/adc8 amp1+/adc9 adc10 amp0- amp0+ - + amp0csr - + amp1csr + - sar 10 10 adch adcl coarse/fine d ac 10 internal 2.56v reference refs0 refs1 aref avc c prescaler ck ck adc con trol ck adc adc c onversion com plete irq gnd bandgap adate adts3 - 224 at90pwm216/316 [datasheet] 7710h?avr?07/2013 20.2 operation the adc converts an analog input voltage to a 10-bit di gital value through successive approximation. the mini- mum value represents gnd and the maximum value r epresents the voltage on the aref pin minus 1 lsb. optionally, av cc or an internal 2.56v reference voltage may be connected to the aref pin by writing to the refsn bits in the admux register. the intern al voltage reference may thus be decoupled by an external capacitor at the aref pin to improve noise immunity. the analog input channel are selected by writing to the mu x bits in admux. any of the adc input pins, as well as gnd and a fixed bandgap voltage reference, can be selected as single ended inputs to the adc. the adc is enabled by setting the adc enable bit, aden in adcsra. voltage reference is set by the refs1 and refs0 bits in admux register, whatever the adc is enabled or not. the adc does not consume power when aden is cleared, so it is recommended to switch off the adc before entering power saving sleep modes. the adc generates a 10-bit result which is presented in the adc data registers, adch and adcl. by default, the result is presented right adjust ed, but can optionally be presented left adjusted by setting the adlar bit in admux. if the result is left adjusted and no more than 8-bit precisio n is required, it is sufficie nt to read adch. otherwise, adcl must be read first, then adch, to ensure that the content of the data registers bel ongs to the same conver- sion. once adcl is read, adc access to data registers is blocked. this means that if adcl has been read, and a conversion completed before adch is re ad, neither register is updated and t he result from the conversion is lost. when adch is read, adc access to the ad ch and adcl registers is re-enabled. the adc has its own interrupt which can be triggered when a conversion completes. the adc access to the data registers is prohibited betw een reading of adch and adcl , the interrupt will tr igger even if the result is lost. 20.3 starting a conversion a single conversion is started by writing a logical one to the adc start conversion bit, adsc. this bit stays high as long as the conversion is in progress and will be cleared by hardware when the conversion is completed. if a differ- ent data channel is selected while a conv ersion is in progress, the adc will finish the current conversion before performing the channel change. alternatively, a conversion can be triggered automatically by various sources. auto triggering is enabled by setting the adc auto trigger enable bit, adate in adcsra. the trigger source is selected by setting the adc trigger select bits, adts in adcsrb (see description of the ad ts bits for a list of the trigger sources). when a positive edge occurs on the selected trigger signal, the adc prescale r is reset and a conversion is started. this provides a method of starting conversions at fixed intervals. if the trigger signal is still set w hen the conversion completes, a new conversion will not be star ted. if another positive ed ge occurs on the trigger signa l during conversion, the edge will be ignored. note that an interrupt flag will be set even if the spec ific interrupt is disabled or the global interrupt enable bit in sreg is cleared. a conv ersion can thus be triggered without causing an interrupt. however, the inter- rupt flag must be cleared in order to trigger a new conversion at the next interrupt event. 225 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 20-2. adc auto trigger logic using the adc interrupt flag as a trigger source make s the adc start a new conversion as soon as the ongoing conversion has finished. the adc then operates in free running mode, co nstantly sampling and updating the adc data register. the first conversion must be started by writing a logical one to the adsc bit in adcsra. in this mode the adc will perform successi ve conversions independen tly of whether the adc interrupt flag, adif is cleared or not. the free running mode is not allowed on the amplified channels. if auto triggering is enabled, single conversions can be started by writing adsc in adcsra to one. adsc can also be used to determine if a conversion is in progres s. the adsc bit will be r ead as one duri ng a conversion, independently of how the conversion was started. 20.4 prescaling and conversion timing figure 20-3. adc prescaler by default, the successive approximation circuitry requi res an input clock frequency between 50 khz and 2 mhz to get maximum resolution. if a lower resolution than 10 bi ts is needed, the input clock frequency to the adc can be higher than 2 mhz to get a higher sample rate. the adc module contains a prescale r, which generates an ac ceptable adc clock frequency from any cpu fre- quency above 100 khz. the prescaling is set by the adps bits in adcsra. th e prescaler starts counting from the moment the adc is switched on by setting the aden bit in adcsra. the prescaler keeps running for as long as the aden bit is set, and is continuously reset when aden is low. when initiating a single ended conversion by setting the adsc bit in adcsra, the conversion starts at the follow- ing rising edge of the adc clock cycle. see ?changing channel or reference selection? on page 227 for details on differential conversion timing. adsc adif source 1 source n adts[2:0] conversion logic prescaler start clk adc . . . . edge detector adate 7-bit adc prescaler adc clock source ck adps0 adps1 adps2 ck/128 ck/2 ck/4 ck/8 ck/16 ck/32 ck/64 reset aden start 226 at90pwm216/316 [datasheet] 7710h?avr?07/2013 a normal conversion takes 13 adc clo ck cycles. the first conversion after the adc is switched on (aden in adc- sra is set) takes 25 adc clock cycles in order to initialize the analog circuitry. the actual sample-and-hold takes place 3.5 adc clock cycl es after the start of a normal conversion and 13.5 adc clock cycles after the start of an first conversion. when a c onversion is complete, the result is written to the adc data registers, and adif is set. in single conversion mode, adsc is cleared simultaneo usly. the software may then set adsc again, and a new conversion will be initia ted on the first rising adc clock edge. when auto triggering is used, the prescaler is reset when the trigger event occurs. this assures a fixed delay from the trigger event to the start of co nversion. in this mode, the sample-and-hold ta kes place two adc clock cycles after the rising edge on the trigger source signal. three additional cpu clock cycles are used for synchronization logic. in free running mode, a new conver sion will be started immedi ately after the conversion completes, while adsc remains high. for a summary of conversion times, see table 20-1 . figure 20-4. adc timing diagram, first conver sion (single conversion mode) figure 20-5. adc timing diagram, single conversion sign and msb of result lsb of result adc clock adsc sample & hold adif adch adcl cycle number aden 1 212 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 first conversion next conversion 3 mux and refs update mux and refs update conversion complete 4 5 6 7 8 9 10 11 12 13 14 15 16 sign and msb of result lsb of result adc clock adsc adif adch adcl cycle number 12 one conversion next conversion 3 sample & hold mux and refs update conversion complete mux and refs update 1 2 3 227 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 20-6. adc timing diagram, auto triggered conversion figure 20-7. adc timing diagram, free running conversion 20.5 changing channel or reference selection the muxn and refs1:0 bits in the admux register are si ngle buffered through a temporary register to which the cpu has random access. this ensures that the channels and reference selection only takes place at a safe point during the conversion. the channel and reference selectio n is continuously updated unti l a conversion is started. once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the adc. continuous updating resumes in the last adc clock cycle before the conversion completes (adif in adcsra is set). note that the conversion starts on the following rising adc clock edge after adsc is written. the user is thus advised not to write new channel or refe rence selection values to admux until one adc clock cycle after adsc is written. if auto triggering is used, the exact time of the triggerin g event can be indeterministic. special care must be taken when updating the admux register, in order to control which conversion w ill be affected by the new settings. table 20-1. adc conversion time condition first conversion normal conversion, single ended auto triggered conversion sample & hold (cycles from start of conversion) 13.5 3.5 4 conversion time (cycles) 25 15.5 16 1 2 3 4 5 6 7 8 13 14 15 16 sign and msb of result lsb of result adc clock trigger source adif adch adcl cycle number 12 one conversion next conversion conversion complete prescaler reset adate prescaler reset sample & hold mux and refs update 14 15 16 sign and msb of result lsb of result adc clock adsc adif adch adcl cycle number 12 one conversion next conversion 34 conversion complete sample & hold mux and refs update 228 at90pwm216/316 [datasheet] 7710h?avr?07/2013 if both adate and aden is written to one, an interrupt event can occur at any time. if the admux register is changed in this period, the user cannot tell if the next co nversion is based on the old or the new settings. admux can be safely updated in the following ways: a. when adate or aden is cleared. b. during conversion, minimum one adc clock cycle after the trigger event. c. after a conversion, before the interrupt flag used as trigger source is cleared. when updating admux in one of th ese conditions, the new settings will affect the next adc conversion. 20.5.1 adc input channels when changing channel selections, the user should observe the following guid elines to ensure that the correct channel is selected: ? in single conversion mode, always select the channel be fore starting the conversion. the channel selection may be changed one adc clock cycle after writing one to adsc. however, the simplest method is to wait for the conversion to complete before changing the channel selection. ? in free running mode, always select the channel before starting the first conversion. the channel selection may be changed one adc clock cycle after writing one to adsc. however, the simplest method is to wait for the first conversion to complete, and then change the channel selection. si nce the next conversion has already started automatically, the nex t result will reflect the previous channel selection. subsequent conversions will reflect the new channel selection. ? in free running mode, because the amplifier clear the adsc bit at the end of an amplified conversion, it is not possible to use the free running mode, unless adsc bit is set again by soft at the end of each conversion. 20.5.2 adc voltage reference the reference voltage for the adc (v ref ) indicates the conversion range for the adc. single ended channels that exceed v ref will result in code s close to 0x3ff. v ref can be selected as either av cc , internal 2.56v reference, or external aref pin. av cc is connected to the adc through a passive switch. the internal 2.56v reference is generated from the inter- nal bandgap reference (v bg ) through an internal amplifier. in either case, the external aref pin is directly connected to the adc, and the reference voltage can be made more immune to noise by connecting a capacitor between the aref pin and ground. v ref can also be measured at the aref pin with a high impedant voltmeter. note that v ref is a high impedant source, and only a capacitive load should be connected in a system. if the user has a fixed voltage source connected to the aref pin, the user may not use the other reference voltage options in the application, as they will be shorted to the external voltage. if no external voltage is applied to the aref pin, the user may switch between av cc and 2.56v as reference selecti on. the first adc conversion result after switching reference voltage source may be inaccura te, and the user is advised to discard this result. if differential channels are used, the selected reference should not be closer to av cc than indicated in table 25-5 on page 289 . 20.6 adc noise canceler the adc features a noise canceler that enables conversion during sleep m ode to reduce noise induced from the cpu core and other i/o peripherals. the noise canceler can be used with adc noise reduction and idle mode. to make use of this feature, the following procedure should be used: 229 at90pwm216/316 [datasheet] 7710h?avr?07/2013 a. make sure the adate bit is reset b. make sure that the adc is enabled and is not busy converting. single co nversion mode must be selected and the adc conversion complete interrupt must be enabled. c. enter adc noise reduction mode (or idle mode). th e adc will start a conversion once the cpu has been halted. d. if no other interrupts occur be fore the adc conversion completes, the adc inte rrupt will wake up the cpu and execute the adc conversion complete inte rrupt routine. if another interrupt wakes up the cpu before the adc conversion is co mplete, that interrupt will be ex ecuted, and an adc conversion complete interrupt request will be generated when the adc c onversion completes. the cpu will remain in active mode until a new sleep command is executed. note that the adc will not be automatically turned o ff when entering other sleep m odes than idle mode and adc noise reduction mode. the user is advised to write zero to aden before entering such sleep modes to avoid excessive power consumption. if the adc is enabled in such sleep modes and the user wants to perform differential conversions, the user is advised to switch the adc off and on after waking up from sleep to prompt an extend ed conversion to get a valid result. 20.6.1 analog input circuitry the analog input circuitry for single end ed channels is illustrated in figure 20- 8. an analog source applied to adcn is subjected to the pin capacitance and input leakage of t hat pin, regardless of whether that channel is selected as input for the adc. when the channel is selected, the sour ce must drive the s/h capacitor through the series resis- tance (combined resistance in the input path). the adc is optimized for analo g signals with an output impedance of approximately 10 k ? or less. if such a source is used, the sampling time will be negligible. if a source with higher impedance is used, the sampling time will depend on how long time the source needs to charge the s/h capacitor, with can vary widely. the user is recom- mended to only use low impedant sources with slowly va rying signals, since this mi nimizes the required charge transfer to the s/h capacitor. if differential gain channels are used, the input circuitry lo oks somewhat different, although source impedances of a few hundred k ? or less is recommended. signal components higher than the nyquist frequency (f adc /2) should not be present for either kind of channels, to avoid distortion from unpredictable si gnal convolution. the us er is advised to remove high frequency components with a low-pass filter before applyi ng the signals as inputs to the adc. figure 20-8. analog input circuitry 20.6.2 analog noise canceling techniques digital circuitry inside and outside the device generates emi which might affect the accuracy of analog measure- ments. if conversion accuracy is critical, the noise leve l can be reduced by applying the following techniques: adcn i ih 1..100 k c s/h = 14 pf v cc /2 i il 230 at90pwm216/316 [datasheet] 7710h?avr?07/2013 a. keep analog signal paths as short as possible. ma ke sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks. b. the av cc pin on the device should be connected to the digital v cc supply voltage via an lc network as shown in figure 20-9 . c. use the adc noise canceler function to reduce induced noise from the cpu. d. if any adc port pins are used as digital outputs, it is essential that these do not switch while a conver- sion is in progress. figure 20-9. adc power connections 20.6.3 offset compensation schemes the gain stage has a built-in offset canc ellation circuitry that nulls the offset of differential measurements as much as possible. the remaining offset in th e analog path can be measured directly by shortening both differential inputs using the ampxis bit with both inputs unconnected. ( see ?amplifier 0 control and st atus register ? amp0csr? on page 243. and see ?amplifier 1control and status register ? amp1csr? on page 244. ). this offset residue can be then subtracted in software from the measurement results. us ing this kind of software based offset correction, off- set on any channel can be reduced below one lsb. 20.6.4 adc accuracy definitions an n-bit single-ended adc converts a voltage linearly between gnd and v ref in 2 n steps (lsbs). the lowest code is read as 0, and the highest code is read as 2 n -1. several parameters describe the deviation from the ideal behavior: ? offset: the deviation of the first transition (0x000 to 0x 001) compared to the ideal transition (at 0.5 lsb). ideal value: 0 lsb. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 2 8 27 26 25 24 23 22 21 20 19 1 8 17 v cc g n d (adc0) pe2 (adc1) pd4 pb7(adc4) pb6 (adc7) pb5 (adc6) pc7 (d2a) pb4 (amp0+) pb3 (amp0-) pc6 (adc10/acmp1) aref ag n d a v cc pc5 (adc9/amp1+) pc4 (adc 8 /amp1-) pb2 (adc5) pd7 (acmp0) pd6 (adc3/acmpm) pd5 (adc2/acmp2) 100nf analog ground plane 10 h 231 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 20-10. offset error ? gain error: after adjusting for offset, the gain error is found as the deviation of the last transition (0x3fe to 0x3ff) compared to the ideal transition (at 1.5 lsb below maximum). ideal value: 0 lsb figure 20-11. gain error ? integral non-linearity (inl): after adjusting for offset and gain error, the inl is the maximum deviation of an actual transition compared to an ideal transition for any code. ideal value: 0 lsb. output code v ref input voltage ideal adc actual adc offset error output code v ref input voltage ideal adc actual adc gain error 232 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 20-12. integral non- linearity (inl) ? differential non-linearity (dnl): the maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 lsb). ideal value: 0 lsb. figure 20-13. differential non-linearity (dnl) ? quantization error: due to the quantiz ation of the input voltage into a finite number of codes, a range of input voltages (1 lsb wide) will code to the same value. always 0.5 lsb. ? absolute accuracy: the maximum deviatio n of an actual (unadjusted) transiti on compared to an ideal transition for any code. this is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. ideal value: 0.5 lsb. 20.7 adc conversion result after the conversion is complete (adif is high), the co nversion result can be found in the adc result registers (adcl, adch). for single ended conversion, the result is: output code v ref input voltage ideal adc actual adc inl output code 0x3ff 0x000 0 v ref input voltage dnl 1 lsb 233 at90pwm216/316 [datasheet] 7710h?avr?07/2013 where v in is the voltage on the selected input pin and v ref the selected voltage reference (see table 20-3 on page 235 and table 20-4 on page 235 ). 0x000 represents analog ground, and 0x 3ff represents the selected reference voltage. if differential channels are used, the result is: where v pos is the voltage on the positive input pin, v neg the voltage on the negative input pin, gain the selected gain factor and v ref the selected voltage reference. the result is presented in two?s complement form, from 0x200 (-512d) through 0x1ff (+511d). note that if the user wants to perform a quick pol arity check of the result, it is suffi- cient to read the msb of the result (adc9 in adch). if the bit is one, the result is negative, and if this bit is zero, the result is positive. figure 20-14 shows the decoding of the differential input range. table 82 shows the resulting output codes if the different ial input channel pair (adcn - adcm) is selected with a reference voltage of v ref . figure 20-14. differential measurement range adc v in 1023 ? v ref -------------------------- = adc v pos v neg ? ?? gain 512 ?? v ref ------------------------------------------------------------------------ = 0 output code 0x1ff 0x000 v ref differential input voltage (volts) 0x3ff 0x200 - v ref /gain /gain 234 at90pwm216/316 [datasheet] 7710h?avr?07/2013 example 1: ? admux = 0xed (adc3 - adc2, 10x gain, 2. 56v reference, left adjusted result) ? voltage on adc3 is 300 mv, voltage on adc2 is 500 mv. ? adcr = 512 * 10 * (300 - 500) / 2560 = -400 = 0x270 ? adcl will thus read 0x00, and adch will read 0x9c. writing zero to adlar right adjusts the result: adcl = 0x70, adch = 0x02. example 2: ? admux = 0xfb (adc3 - adc2, 1x gain, 2.56v reference, left adjusted result) ? voltage on adc3 is 300 mv, voltage on adc2 is 500 mv. ? adcr = 512 * 1 * (300 - 500) / 2560 = -41 = 0x029 . ? adcl will thus read 0x40, and adch will read 0x0a. writing zero to adlar right adjusts the result: adcl = 0x00, adch = 0x29. 20.8 adc register description the adc of the at90pwm216/316 is controlled throug h 3 different registers. the adcsra and the adcsrb registers which are the adc control and status registers, and the admux which allows to select the vref source and the channel to be converted. the conversion result is st ored on adch and adcl register which cont ain respectively the most significant bits and the less significant bits. table 20-2. correlation between input voltage and output codes v adcn read code corresponding decimal value v adcm + v ref /gain 0x1ff 511 v adcm + 0.999 v ref /gain 0x1ff 511 v adcm + 0.998 v ref /gain 0x1fe 510 ... ... ... v adcm + 0.001 v ref /gain 0x001 1 v adcm 0x000 0 v adcm - 0.001 v ref /gain 0x3ff -1 ... ... ... v adcm - 0.999 v ref /gain 0x201 -511 v adcm - v ref /gain 0x200 -512 235 at90pwm216/316 [datasheet] 7710h?avr?07/2013 20.8.1 adc multiplexer register ? admux ? bit 7, 6 ? refs1, 0: adc vref selection bits these 2 bits determine the voltage reference for the adc. the different setting are shown in table 20-3 . if these bits are changed during a conver sion, the change will not take effect un til this conversion is complete (it means while the adif bit in adcsra register is set). in case the internal vref is selected, it is turned on as soon as an analog feature needed it is set. ? bit 5 ? adlar: adc left adjust result set this bit to left adjust the adc result. clear it to right adjust the adc result. the adlar bit affects the configuration of the adc result data registers. changing this bit affects the adc data registers immediately regardless of any on going conver sion. for a complete description of this bit, see section ?adc result data regist ers ? adch and adcl?, page 238. ? bit 3, 2, 1, 0 ? mux3, mux2, mu x1, mux0: adc channel selection bits these 4 bits determine which analog inputs are connected to the adc input. the different setting are shown in table 20-4 . bit 76543210 refs1 refs0 adlar - mux3 mux2 mux1 mux0 admux read/write r/w r/w r/w - r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 20-3. adc voltage reference selection refs1 refs0 description 0 0 external vref on aref pin, in ternal vref is switched off 0 1 avcc with external capacitor connected on the aref pin 10reserved 11 internal 2.56v reference voltage with external capacitor connected on the aref pin table 20-4. adc input chan nel selection mux3 mux2 mux1 mux0 description 0000adc0 0001adc1 0010adc2 0011adc3 0100adc4 0101adc5 0110adc6 0111adc7 1000adc8 1001adc9 1010adc10 236 at90pwm216/316 [datasheet] 7710h?avr?07/2013 if these bits are changed during a conver sion, the change will not take effect un til this conversion is complete (it means while the adif bit in adcsra register is set). 20.8.2 adc control and stat us register a ? adcsra ? bit 7 ? aden: adc enable bit set this bit to enable the adc. clear this bit to disable the adc. clearing this bit while a conversion is running will take effect at the end of the conversion. ? bit 6? adsc: adc start conversion bit set this bit to start a conversion in single conversion mode or to start the first conversion in free running mode. cleared by hardware when the conversion is comp lete. writing this bit to zero has no effect. the first conversion performs the initialization of the adc. ? bit 5 ? adate: adc auto trigger enable bit set this bit to enable the auto triggering mode of the adc. clear it to return in single conversion mode. in auto trigger mode the trigger source is selected by the adts bits in the adcsrb register. see table 20-6 on page 237 . ? bit 4? adif: adc interrupt flag set by hardware as soon as a conversion is complete and the data register are updated with the conversion result. cleared by hardware when executing the corresponding interrupt handling vector. alternatively, adif can be cleared by writing it to logical one. ? bit 3? adie: adc interrupt enable bit set this bit to activate the a dc end of conversion interrupt. clear it to disable the adc end of conversion interrupt. ? bit 2, 1, 0? adps2, adps1, ad ps0: adc prescaler selection bits these 3 bits determine the division factor between the system clock frequency and input clock of the adc. the different setting are shown in table 20-5 . 1011amp0 1100amp1 (- is adc8, + is adc9) 1101reserved 1110bandgap 1111gnd table 20-4. adc input chan nel selection mux3 mux2 mux1 mux0 description bit 76543210 aden adsc adate adif adie adps2 adps1 adps0 adcsra read/write r/w r/w r/w r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 237 at90pwm216/316 [datasheet] 7710h?avr?07/2013 20.8.3 adc control and stat us register b? adcsrb ? bit 7 ? adhsm: adc high speed mode writing this bit to one enables the adc high speed mode. se t this bit if you wish to convert with an adc clock fre- quency higher than 200khz. ? bit 3, 2, 1, 0? adts3:adts0: adc auto trigger source selection bits these bits are only necessary in case the adc works in auto trigger mode. it means if adate bit in adcsra reg- ister is set. in accordance with the table 20- 6, these 3 bits select the interrupt event whic h will generate the tr igger of the start of conversion. the start of conversion will be generated by the rising edge of the selected interrup t flag whether the interrupt is enabled or not. in case of trig on pscnasy ev ent, there is no flag. so in this case a conversion will start each time the trig event appears and the previous conversion is completed.. table 20-5. adc prescaler selection adps2 adps1 adps0 division factor 0002 0012 0104 0118 10016 10132 11064 111128 bit 76543210 adhsm - - - adts3 adts2 adts1 adts0 adcsrb read/write - - - - r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 20-6. adc auto trigger source selection for non amplified conversions adts3 adts2 adts1 adts0 description 0 0 0 0 free running mode 0 0 0 1 analog comparator 0 0 0 1 0 external interrupt request 0 0 0 1 1 timer/counter0 compare match 0 1 0 0 timer/counter0 overflow 0 1 0 1 timer/counter1 compare match b 0 1 1 0 timer/counter1 overflow 0 1 1 1 timer/counter1 capture event 1 0 0 0 psc0asy event (1) 1 0 0 1 psc1asy event 1 0 1 0 psc2asy event 238 at90pwm216/316 [datasheet] 7710h?avr?07/2013 . 20.8.4 adc result data registers ? adch and adcl when an adc conversion is complete, the conversion re sults are stored in these two result data registers. when the adcl register is read, the two adc result data registers can?t be updated until the adch register has also been read. consequently, in 10-bit configuration, the adcl register must be read first before the adch. nevertheless, to work easily with only 8-bit precision, there is the possibility to left adjust the re sult thanks to the adlar bit in the adcsra register. like this, it is suffi cient to only read adch to have the conversion result. 20.8.4.1 adlar = 0 20.8.4.2 adlar = 1 1 0 1 1 analog comparator 1 1 1 0 0 analog comparator 2 1101reserved 1110reserved 1111reserved 1. for trigger on any psc event, if the psc uses the pll clock, the core must use pll/4 clock source table 20-7. adc auto trigger sour ce selection for am plified conversions adts3 adts2 adts1 adts0 description 0 0 0 0 free running mode 1 0 0 0 psc0asy event (1) 1. for trigger on any psc event, if the psc uses the pll clock, the core must use pll/4 clock source 1 0 0 1 psc1asy event 1 0 1 0 psc2asy event table 20-6. adc auto trigger source selection for non amplified conversions adts3 adts2 adts1 adts0 description bit 76543210 - - - - - - adc9 adc8 adch adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 adcl read/write r r r r r r r r rrrrrrrr initial value 0 0 0 0 0 0 0 0 00000000 bit 76543210 adc9 adc8 adc7 adc6 adc5 adc4 adc3 adc2 adch adc1 adc0 - - - - - - adcl read/write r r r r r r r r rrrrrrrr initial value 0 0 0 0 0 0 0 0 00000000 239 at90pwm216/316 [datasheet] 7710h?avr?07/2013 20.8.5 digital input disa ble register 0 ? didr0 ? bit 7:0 ? adc7d..adc0d: acmp2:1 and adc7:0 digital input disable when this bit is written logic one, the digital input bu ffer on the corresponding adc pin is disabled. the corre- sponding pin register bit will always read as zero when this bit is set. when an analog signal is applied to the adc7..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 20.8.6 digital input disa ble register 1? didr1 ? bit 5:0 ? acmp0d, amp0+d, amp0-d, adc10d..adc 8d: acmp0, amp1:0 and adc10:8 digital input disable when this bit is written logic one, the digital input bu ffer on the corresponding adc pin is disabled. the corre- sponding pin register bit will always read as zero when this bit is set. when an analog signal is applied to an analog pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power con- sumption in the di gital input buffer. 20.9 amplifier the at90pwm216/316 features two differential amplified channels with programmable 5, 10, 20, and 40 gain stage. despite the result is given by the 10 bit adc, the amplifier has been sized to give a 8bits resolution. because the amplifier is a switching capa citor amplifier, it needs to be clocke d by a synchronization signal called in this document the amplifier synchronization clock. the maximum frequency of this clock is 250khz. to ensure an accurate result, the amplifier input needs to have a quite stable input value at the sampling point dur- ing at least 4 amplifier synchronization clock periods. amplified conversions can be sy nchronized to psc events (see ?synchronization source description in one/two/four ramp modes? on page 154 and ?synchronization source description in centered mode? on page 154 ) or to the internal clock ck adc equal to eighth the adc clock frequency. in case the synchronization is done by the adc clock divided by 8, this synchronization is done au tomatically by the adc interf ace in such a way that the sample-and-hold occurs at a specific phase of ck adc2 . a conversion initiated by the user (i.e., all single conver- sions, and the first free running conversion) when ck adc2 is low will take the same amount of time as a single ended conversion (13 adc clock c ycles from the next presca led clock cycle). a conver sion initiated by the user when ck adc2 is high will take 14 adc clock cycles due to the synchroni zation mechanism. the normal way to use the amplifier is to select a synchronization clock via the ampxts1:0 bits in the ampxcsr register. then the amplifier can be switched on, and the am plification is done on each synchronization event. the amplification is done i ndependently of the adc. in order to start an amplified analog to digital conversion on the amplified channel, the admux must be config- ured as specified on table 20-4 on page 235 . the adc starting is done by setting the adsc (a dc start conversion) bit in the adcsra register. bit 76543210 adc7d adc6d adc5d adc4d adc3d acmpm adc2d acmp2d adc1d adc0d didr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 bit 76543210 - - acmp0d amp0pd amp0nd adc10d acmp1d adc9d amp1pd adc8d amp1nd didr1 read/write - - r/w r/w r/w r/w r/w r/w initial value 00000000 240 at90pwm216/316 [datasheet] 7710h?avr?07/2013 until the conversion is not achieved, it is not po ssible to start a conversion on another channel. the conversion takes advantage of the amplifier ch aracteristics to ensure minimum conversion time. as soon as a conversion is requested thanks to the adsc bi t, the analog to digital conv ersion is started. in order to have a better understanding of the functioning of t he amplifier synchronization, a timing diagram example is shown figure 20-15 . in case the amplifier output is modified during the samp le phase of the adc, the on-going conversion is aborted and restarted as soon as the output of the amplifier is stable as shown figure 20-16 . the only precaution to take is to be sure that the trig signal (psc) frequenc y is lower than adcclk/4. t is also possible to auto trigger conversion on the amplif ied channel. in this case, the conversion is started at the next amplifier clock event following the last auto trigger event selected thanks to the adts bits in the adcsrb register. in auto trigger conversion, the free running mode is not possible unless the adsc bit in adcsra is set by soft after each conversion. only psc sources can auto trigger amplified conversion. in this case, the core must have a clock synchronous with the psc; if the psc uses the pll clock, the core must use pll/4 clock source. figure 20-15. amplifier synchronization timing diagra m with change on analog input signal. valid sample delta v 4th stable sample signal to be measured ampli_clk (sync clock) ck adc2 amplifier sample enable amplifier hold value pscn_asy psc block a mplifier block adsc adc activity adc adc sampling adc conv adc sampling adc conv adc result ready adc resu lt ready 241 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 20-16. amplifier synchronization timing diagram: behavior when adsc is set when theamplifier output is changing. the block diagram of the two amplifiers is shown on figure 20-17 . valid sample signal to be measured ampli_clk (sync clock) ck adc2 amplifier sample enable amplifier hold value pscn_asy psc block amplifier block adsc adc activity adc adc sampling adc conv adc sampling adc conv adc sampling aborted adc result ready adc result ready 242 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 20-17. amplifiers block diagram amp0ts1 amp0ts0 amp0en amp0is amp0g1 amp0g0 amp0csr + - sampling amp0+ amp0- toward adc mux (amp0) sampling clock adck/8 01 10 01 00 psc0asy psc1asy psc2asy -- amp1ts1 amp1ts0 amp1en amp1is amp1g1 amp1g0 amp1csr + - sampling amp1+ amp1- toward adc mu (amp1) sampling clock adck/8 01 10 01 00 -- psc0asy psc1asy psc2asy 243 at90pwm216/316 [datasheet] 7710h?avr?07/2013 20.10 amplifier c ontrol registers the configuration of the amplifiers are controlled via two dedicated registers amp0csr and amp1csr. then the start of conversion is done via the adc control and status registers. the conversion result is st ored on adch and adcl register which cont ain respectively the most significant bits and the less significant bits. 20.10.1 amplifier 0 control and status register ? amp0csr ? bit 7 ? amp0en: amplifier 0 enable bit set this bit to enable the amplifier 0. clear this bit to di sable the amplifier 0. clearing this bit while a conversion is running will take effect at the end of the conversion. warning: always clear ampnts0:1 when clearing ampxen ? bit 6? amp0is: amplifier 0 input shunt set this bit to short-circuit the amplifier 0 input. clear this bit to norma lly use the amplifier 0. ? bit 5, 4? amp0g1, 0: ampl ifier 0 gain selection bits these 2 bits determine the gain of the amplifier 0. the different setting are shown in table 20-8 . to ensure an accurate result, after the gain value has been changed, the amplifier input needs to have a quite sta- ble input value during at least 4 amplifier synchronization clock periods. ? bit 1, 0? amp0ts1, amp0ts0: amplifier 0 trigger source selection bits in accordance with the table 20-9, these 2 bits select the event which will generate th e trigger for th e amplifier 0. this trigger source is necessary to start the conversion on the amplified channel. bit 76543210 amp0en amp0is amp0g1 amp0g0 - - amp0ts1 amp0ts0 amp0csr read/write r/w r/w r/w r/w - - r/w r/w initial value 0 0 0 0 0 0 0 0 table 20-8. amplifier 0 gain selection amp0g1 amp0g0 description 00gain 5 01gain 10 10gain 20 11gain 40 table 20-9. amp0 auto trigger source selection amp0ts1 amp0ts0 description 0 0 auto synchronization on adc clock/8 0 1 trig on psc0asy 1 0 trig on psc1asy 1 1 trig on psc2asy 244 at90pwm216/316 [datasheet] 7710h?avr?07/2013 20.10.2 amplifier 1control and status register ? amp1csr ? bit 7 ? amp1en: amplifier 1 enable bit set this bit to enable the amplifier 1. clear this bit to di sable the amplifier 1. clearing this bit while a conversion is running will take effect at the end of the conversion. warning: always clear ampnts0:1 when clearing ampxen ? bit 6? amp1is: amplifier 1 input shunt set this bit to short-circuit the amplifier 1 input. clear this bit to norma lly use the amplifier 1. ? bit 5, 4? amp1g1, 0: ampl ifier 1 gain selection bits these 2 bits determine the gain of the amplifier 0. the different setting are shown in table 20-10 . to ensure an accurate result, after the gain value has been changed, the amplifier input needs to have a quite sta- ble input value during at least 4 amplifier synchronization clock periods. ? bit 1, 0? amp1ts1, amp1ts0: amplifier 1 trigger source selection bits in accordance with the table 20-11, thes e 2 bits select the event which will gen erate the trigger for the amplifier 1. this trigger source is necessary to star t the conversion on the amplified channel. bit 76543210 amp1en amp1is amp1g1 amp1g0 - - amp1ts1 amp1ts0 amp1csr read/write r/w r/w r/w r/w - - r/w r/w initial value 0 0 0 0 0 0 0 0 table 20-10. amplifier 1 gain selection amp1g1 amp1g0 description 00gain 5 01gain 10 10gain 20 11gain 40 table 20-11. amp1 auto trigger source selection amp1ts1 amp1ts0 description 0 0 auto synchronization on adc clock/8 0 1 trig on psc0asy 1 0 trig on psc1asy 1 1 trig on psc2asy 245 at90pwm216/316 [datasheet] 7710h?avr?07/2013 21. digital to analog converter - dac 21.1 features ? 10 bits resolution ? 8 bits linearity ? +/- 0.5 lsb accuracy between 150mv and avcc-150mv ? vout = dac*vref/1023 ? the dac could be connected to the negati ve inputs of the analog comparators and/or to a dedicated output driver. ? output impedance around 100 ohm. the at90pwm216/316 features a 10-bit digital to analog converter. this dac can be used for the analog com- parators and/or can be output on the d2a pin of the microcontroller via a dedicated driver. this allow to drive (worst case) a 1nf capacitance in pa rallel with a resistor higher than 33k load with a time con- stant around 1us. response time and power consumption are improved by reducing the load (reducing the capacitor value and increasing the load resistor value (the best case is a high impedance)). the dac has a separate analog supply voltage pin, av cc . av cc must not differ more than 0.3v from v cc . see the paragraph ?adc noise canceler? on page 228 on how to connect this pin. the reference voltage is the same as the one used for the adc, see ?adc multiplexer register ? admux? on page 235. . these nominally 2.56v vref or av cc are provided on-chip. the vo ltage reference may be externally decoupled at the aref pin by a capa citor for better noise performance. figure 21-1. digital to analog converter block schematic dac output driver dala daoe daen - daate dats2 dats1 dats0 10 dach dacl dacon 10 10 10 vref d2a pin dac result update dac trigger dac low bits dac high bits edge detector sources 246 at90pwm216/316 [datasheet] 7710h?avr?07/2013 21.2 operation the digital to analog converter generat es an analog signal proportional to the value of the dac registers value. in order to have an accurate sampling frequency control, there is the possibility to update the dac input values through different trigger events. 21.3 starting a conversion the dac is configured thanks to the dacon register. as so on as the daen bit in dacon register is set, the dac converts the value present on the dach and dacl regi sters in accordance with the register dacon setting. alternatively, a conversion can be triggered automatically by various sources. auto triggering is enabled by setting the dac auto trigger enable bit, daate in dacon. the tr igger source is selected by setting the dac trigger select bits, dats in dacon (see descr iption of the dats bits for a list of the trigger sources). when a positive edge occurs on the selected trigger signal, the dac co nverts the value present on the dach and dacl registers in accordance with the register dacon setting. this provid es a method of starting conver sions at fixed intervals. if the trigger signal is still set when the conversion completes, a new conversion will not be started. if another positive edge occurs on the trigger si gnal during conversion, the edge will be ignored. note th at an interrup t flag will be set even if the specific interrupt is dis abled or the global interrupt enable bit in sreg is cleared. a conversion can thus be triggered without causing an interrupt. however, the interrupt flag must be cleared in order to trigger a new conversion at the next interrupt event. 21.3.1 dac voltage reference the reference voltage for the adc (v ref ) indicates the conversion range for the dac. v ref can be selected as either av cc , internal 2.56v reference, or external aref pin. av cc is connected to the dac through a passive switch. the internal 2.56v reference is generated from the inter- nal bandgap reference (v bg ) through an internal amplifier. in either case, the external aref pin is directly connected to the dac, and the reference voltage can be made more immune to noise by connecting a capacitor between the aref pin and ground. v ref can also be measured at the aref pin with a high impedant voltmeter. note that v ref is a high impedant source, and only a capacitive load should be connected in a system. if the user has a fixed voltage source connected to the aref pin, the user may not use the other reference voltage options in the application, as they will be shorted to the external voltage. if no external voltage is applied to the aref pin, the user may switch between av cc and 2.56v as reference selecti on. the first dac conversion result after switching reference voltage source may be inaccura te, and the user is advised to discard this result. 21.4 dac register description the dac is controlled via three dedicated registers: ? the dacon register which is used for dac configuration ? dach and dacl which are used to set the value to be converted. 21.4.1 digital to analog conversion control register ? dacon ? bit 7 ? daate: dac auto trigger enable bit set this bit to update the dac input value on the positive edge of the trigger signal selected with the dacts2-0 bit in dacon register. clear it to automatically update the dac inpu t when a value is writ ten on dach register. bit 76543210 daate dats2 dats1 dats0 - dala daoe daen dacon read/write r/w r/w r/w r/w - r/w r/w r/w initial value 0 0 0 0 0 0 0 0 247 at90pwm216/316 [datasheet] 7710h?avr?07/2013 ? bit 6:4 ? dats2, dats1, dats0: dac trigger selection bits these bits are only necessary in ca se the dac works in auto trigger mo de. it means if daate bit is set. in accordance with the table 21-1 , these 3 bits select the interrupt event whic h will generate the update of the dac input values. the update will be generated by the rising edge of the select ed interrupt flag whet her the interrupt is enabled or not. ? bit 2 ? dala: digital to analog left adjust set this bit to left adju st the dac input data. clear it to right adjust the dac input data. the dala bit affects the conf iguration of the dac data regi sters. changing this bit af fects the dac output on the next dach writing. ? bit 1 ? daoe: digital to analog output enable bit set this bit to output the conversion result on d2a, clear it to use the dac internally. ? bit 0 ? daen: digital to analog enable bit set this bit to enable the dac, clear it to disable the dac. 21.4.2 digital to analog converte r input register ? dach and dacl dach and dacl registers contain the value to be converted into analog voltage. writing the dacl register fo rbid the update of the input value until dach has not been written too. so the normal way to write a 10-bit value in the dac register is firs tly to write dacl the dach. in order to work easily with only 8 bits, there is the possibility to left adjust the input value. like this it is sufficient t o write dach to update the dac value. 21.4.2.1 dala = 0 table 21-1. dac auto trigger source selection dats2 dats1 dats0 description 0 0 0 analog comparator 0 0 0 1 analog comparator 1 0 1 0 external interrupt request 0 0 1 1 timer/counter0 compare match 1 0 0 timer/counter0 overflow 1 0 1 timer/counter1 compare match b 1 1 0 timer/counter1 overflow 1 1 1 timer/counter1 capture event bit 76543210 - - - - - - dac9 dac8 dach dac7 dac6 dac5 dac4 dac3 dac2 dac1 dac0 dacl read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 00000000 248 at90pwm216/316 [datasheet] 7710h?avr?07/2013 21.4.2.2 dala = 1 to work with the 10-bit dac, two registers have to be updat ed. in order to avoid intermediate value, the dac input values which are really converted into analog signal are buffering into unreachable registers. in normal mode, the update of the shadow register is done when the register dach is written. in case daate bit is set, the dac input values will be u pdated on the trigger event se lected through dats bits. in order to avoid wrong dac input values, the update can on ly be done after having written respectively dacl and dach registers. it is possible to work on 8-bit configurat ion by only writing the dach va lue. in this case, update is done each trigger event. in case daate bit is cleared, the dac is in an automatic update mode. writing the dach register automatically update the dac input values with t he dach and dacl register values. it means that whatever is the configuration of the daat e bit, changing the dacl register has no effect on the dac output until the dach register has also been updated. so, to work with 10 bi ts, dacl must be written first before dach. to work with 8-bit configuration, wr iting dach allows the update of the dac. bit 76543210 dac9 dac8 dac7 dac6 dac5 dac4 dac3 dac2 dach dac1 dac0 - - - - - - dacl read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 00000000 249 at90pwm216/316 [datasheet] 7710h?avr?07/2013 22. debugwire on-ch ip debug system 22.1 features ? complete program flow control ? emulates all on-chi p functions, both digital and analog, ex cept reset pin ? real-time operation ? symbolic debugging support (both at c and assembler source level, or for other hlls) ? unlimited number of program break points (using software break points) ? non-intrusive operation ? electrical characteristics identical to real device ? automatic configuration system ? high-speed operation ? programming of non-volatile memories 22.2 overview the debugwire on-chip debug system uses a one-wire, bi-d irectional interface to control the program flow, exe- cute avr instructions in the cpu and to program the different non-volatile memories. 22.3 physical interface when the debugwire enable (dwen) fuse is progra mmed and lock bits are unprogrammed, the debugwire system within the target device is activated. the reset po rt pin is configured as a wire-and (open-dra in) bi-direc- tional i/o pin with pull-up enabled and becomes the communication gateway between target and emulator. figure 22-1. the debugwire setup figure 22-1 shows the schematic of a target mcu, with debugwire enabled, and the emulator connector. the system clock is not affect ed by debugwire and will always be the clock source selected by the cksel fuses. when designing a system where debugwir e will be used, the following observations must be made for correct operation: ? pull-up resistors on the dw/(reset) line must not be smaller than 10k ? . the pull-up resistor is not required for debugwire functionality. ? connecting the reset pin directly to v cc will not work. d w gnd dw(reset) vcc 1.8 - 5.5 v 250 at90pwm216/316 [datasheet] 7710h?avr?07/2013 ? capacitors connected to t he reset pin must be disconnected when using debugwire. ? all external reset sources must be disconnected. 22.4 software break points debugwire supports program memory break points by the avr break instruction. setting a break point in avr studio ? will insert a break instru ction in the program memory. the instru ction replaced by the break instruction will be stored. when program execution is continued, the stored inst ruction will be executed before continuing from the program memory. a break can be in serted manually by putting the break instruction in the program. the flash must be re-programmed each time a break point is changed. this is automa tically handled by avr stu- dio through the debugwire in terface. the use of break points will th erefore reduce the flash data retention. devices used for debugging purposes should not be shipped to end customers. 22.5 limitations of debugwire the debugwire communication pin (dw) is physically located on the same pi n as external reset (reset). an external reset source is therefore not supported when the debugwire is enabled. the debugwire system accurately emulates all i/o functi ons when running at full speed, i.e., when the program in the cpu is running. when the cpu is stopped, care must be taken while ac cessing some of the i/o registers via the debugger (avr studio). a programmed dwen fuse enables some parts of the clock system to be running in all sleep modes. this will increase the power consumption while in sleep. thus, th e dwen fuse should be disabled when debugwire is not used. 22.6 debugwire related re gister in i/o memory the following section describes the registers used with the debugwire. 22.6.1 debugwire data register ? dwdr the dwdr register provides a co mmunication channel from the running program in the mcu to the debugger. this register is only accessible by the debugwire and ca n therefore not be used as a general purpose register in the normal operations. bit 76543210 dwdr[7:0] dwdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 251 at90pwm216/316 [datasheet] 7710h?avr?07/2013 23. boot loader supp ort ? read-while-wri te self-programming in at90pwm216/316, the boot loader support provides a real read-while-write self-programming mechanism for downloading and uploading program code by the mcu it self. this feature allows flexible ap plication software updates controlled by the mcu using a flash-resident b oot loader program. the boot loader program can use any available data interf ace and associated protocol to read code a nd write (program) that code into the flash memory, or read the code from the program memory. th e program code within the boot loader section has the capability to write into the entire flash, including the boot loader memory. the bo ot loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. the size of the boot loader memory is configurable with fuses and the boot loader has two separate sets of boot lock bits which can be set independently. this gives the user a unique flexibility to select different levels of protection. 23.1 boot loader features ? read-while-write self-programming ? flexible boot memory size ? high security (separate boot lock bits for a flexible protection) ? separate fuse to select reset vector ? optimized page (1) size ? code efficient algorithm ? efficient read-modify-write support note: 1. a page is a section in the flash consisting of several bytes (see table 24-11 on page 270 ) used during program- ming. the page organization does not affect normal operation. 23.2 application and boot loader flash sections the flash memory is organized in two main sections, th e application section and t he boot loader section (see fig- ure 23-2 ). the size of the different sections is configured by t he bootsz fuses as shown in table 23-6 on page 263 and figure 23-2 . these two sections can have different level of protection since they have different sets of lock bits. 23.2.1 application section the application section is the section of the flash that is used for storing the application code. the protection level for the application section can be selected by the a pplication boot lock bits (boot lock bits 0), see table 23-2 on page 255 . the application section can never store any boot loader code since the spm instruction is disabled when executed from the application section. 23.2.2 bls ? boot loader section while the application section is used for storing the application code, the the boot loader software must be located in the bls since the spm instruction can initiate a programming when executing from the bls only. the spm instruction can access the entire flash, including the bls itself. the protection level for the boot loader sec- tion can be selected by the boot loader lock bits (boot lock bits 1), see table 23-3 on page 255 . 23.3 read-while-write and no r ead-while-write flash sections whether the cpu supports read-while-write or if the cpu is halted during a boot loader software update is dependent on which address that is being programmed. in add ition to the two sections th at are configurable by the bootsz fuses as described above, th e flash is also divided into two fixed sections, the read-while-write (rww) section and the no read-while -write (nrww) section. the limit between the rww- and nrww sections is given in table 23-7 on page 263 and figure 23-2 on page 254 . the main difference between the two sections is: 252 at90pwm216/316 [datasheet] 7710h?avr?07/2013 ? when erasing or writing a page located inside the rww section, the nrww section can be read during the operation. ? when erasing or writing a page located inside the nr ww section, the cpu is halted during the entire operation. note that the user software can never read any code t hat is located inside the rww section during a boot loader software operation. the syntax ?read-while-write sectio n? refers to which section that is being programmed (erased or written), not which secti on that actually is being read du ring a boot loader software update. 23.3.1 rww ? read-while-write section if a boot loader software update is programming a page in side the rww section, it is possible to read code from the flash, but only code that is located in the nrww se ction. during an on-going programming, the software must ensure that the rww section never is being read. if the us er software is trying to read code that is located inside the rww section (i.e., by a call/jmp/lpm or an interrupt ) during programming, the software might end up in an unknown state. to avoid this, the interrupts should either be disabled or moved to the boot loader section. the boot loader section is always loca ted in the nrww section. the rww section busy bit (rwwsb) in the store program memory control and status r egister (spmcsr) will be read as logi cal one as long as the rww section is blocked for reading. after a programming is completed, the rwwsb must be cleared by software before reading code located in the rww section. see ?store program memory control and status register ? spmcsr? on page 256. for details on how to clear rwwsb. 23.3.2 nrww ? no read -while-write section the code located in the nrww section can be read when the boot loader software is updating a page in the rww section. when the boot loader code updates the nrw w section, the cpu is halted during the entire page erase or page write operation. table 23-1. read-while-write features which section does the z-pointer address during the programming? which section can be read during programming? is the cpu halted? read-while-write supported? rww section nrww section no yes nrww section none yes no 253 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 23-1. read-while-write vs. no read-while-write read-while-write (rww) section no read-while-write (nrww) section z-pointer addresses rww section z-pointer addresses nrww section cpu is halted during the operation code located in nrww section can be read during the operation 254 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 23-2. memory sections note: 1. the parameters in the figure above are given in table 23-6 on page 263 . 23.4 boot loader lock bits if no boot loader capability is needed, the entire flash is available for application c ode. the boot loader has two separate sets of boot lock bits which can be set independ ently. this gives the user a unique flexibility to select dif- ferent levels of protection. the user can select: ? to protect the entire flash from a software update by the mcu. ? to protect only the boot loader flash sect ion from a software update by the mcu. ? to protect only the application flash section from a software update by the mcu. ? allow software update in the entire flash. see table 23-2 and table 23-3 for further details. the boot lock bits can be set in software and in serial or paral- lel programming mode, but they can be cleared by a chip erase command only. the general write lock (lock bit mode 2) does not control the progra mming of the flash memory by spm instruction. similarly, the general read/write lock (lock bit mode 1) do es not control reading nor writing by lpm/spm, if it is attempted. 0x0000 flashend program memory boot s z = '11' application flash section boot loader flash section flashend program memory boot s z = '10' 0x0000 program memory boot s z = '01' program memory boot s z = '00' application flash section boot loader flash section 0x0000 flashend application flash section flashend end rww start nrww application flash section boot loader flash section boot loader flash section end rww start nrww end rww start nrww 0x0000 end rww, end application start nrww, start boot loader application flash section application flash section application flash section read-while-write section no read-while-write section read-while-write section no read-while-write section read-while-write section no read-while-write section read-while-write section no read-while-write section end application start boot loader end application start boot loader end application start boot loader 255 at90pwm216/316 [datasheet] 7710h?avr?07/2013 note: 1. ?1? means unprogrammed, ?0? means programmed note: 1. ?1? means unprogrammed, ?0? means programmed 23.5 entering the boot loader program entering the boot loader takes place by a jump or call from the application program. this may be initiated by a trig- ger such as a command received via usart, or spi in terface. alternatively, the boot reset fuse can be programmed so that the reset vector is pointing to the boot flash start address after a reset. in this case, the boot loader is started after a reset. after the application code is loaded, the program can start executing the application code. note that the fuses cannot be changed by the mcu it self. this means that once the boot reset fuse is pro- grammed, the reset vector will always point to the boot loader rese t and the fuse can only be ch anged through the serial or parallel programming interface. note: 1. ?1? means unprogrammed, ?0? means programmed table 23-2. boot lock bit0 protection modes (application section) (1) blb0 mode blb02 blb01 protection 111 no restrictions for spm or lpm accessing the application section. 2 1 0 spm is not allowed to write to the application section. 300 spm is not allowed to write to the application section, and lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. 401 lpm executing from the boot load er section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. table 23-3. boot lock bit1 protection modes (boot loader section) (1) blb1 mode blb12 blb11 protection 111 no restrictions for spm or lpm accessing the boot loader section. 2 1 0 spm is not allowed to write to the boot loader section. 300 spm is not allowed to write to the boot loader section, and lpm executing from the application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. 401 lpm executing from the applicat ion section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. table 23-4. boot reset fuse (1) bootrst reset address 1 reset vector = application reset (address 0x0000) 0 reset vector = boot loader reset (see table 23-6 on page 263 ) 256 at90pwm216/316 [datasheet] 7710h?avr?07/2013 23.5.1 store program memory control and status register ? spmcsr the store program memory control and status register contains the control bits needed to control the boot loader operations. ? bit 7 ? spmie: spm interrupt enable when the spmie bit is written to one, and the i-bit in the status register is set (one ), the spm ready interrupt will be enabled. the spm ready interrupt will be executed as long as the spmen bit in the spmcsr register is cleared. ? bit 6 ? rwwsb: read-while-write section busy when a self-programming (page erase or page write) operation to the r ww section is initiated, the rwwsb will be set (one) by hardware. when the rwwsb bit is set, the rww section cannot be accessed. the rwwsb bit will be cleared if the rwwsre bit is wri tten to one after a self-programming o peration is completed. alternatively the rwwsb bit will automatically be cleared if a page load oper ation is initiated. ? bit 5 ? res: reserved bit this bit is a reserved bit in the at90pwm216/316 and always read as zero. ? bit 4 ? rwwsre: read-while-write section read enable when programming (page erase or page write) to the rw w section, the rww section is blocked for reading (the rwwsb will be set by hardware). to re-enable the rww sect ion, the user software mu st wait until the program- ming is completed (spmen will be clear ed). then, if the rwwsre bit is wr itten to one at the same time as spmen, the next spm instruction within four clock cycles re-enables the rww secti on. the rww section cannot be re-enabled while the flash is busy with a page erase or a page write (spmen is set). if the rwwsre bit is written while the flash is being l oaded, the flash load o peration will abort and the data loaded will be lost. ? bit 3 ? blbset: boot lock bit set if this bit is written to one at the same time as spmen, the next spm instruction within four clock cycles sets boot lock bits and memory lock bits, according to the data in r0. the data in r1 and the address in the z-pointer are ignored. the blbset bit will au tomatically be cleared upon completion of t he lock bit set, or if no spm instruction is executed within four clock cycles. an lpm instruction within three cycl es after blbset and spmen are set in the spmcsr regist er, will read either the lock bits or the fuse bits (depending on z0 in the z-pointer) into the destination register. see ?reading the fuse and lock bits from software? on page 260 for details. ? bit 2 ? pgwrt: page write if this bit is written to one at the same time as spmen , the next spm instruction within four clock cycles executes page write, with the data st ored in the temporary buffer. the page address is taken from the high part of the z- pointer. the data in r1 and r0 are ig nored. the pgwrt bit will auto -clear upon completion of a page write, or if no spm instruction is executed within four clock cycles. the cpu is halted during the entire page write operation if the nrww section is addressed. ? bit 1 ? pgers: page erase if this bit is written to one at the same time as spmen , the next spm instruction within four clock cycles executes page erase. the page address is taken from the high part of the z-pointer. the data in r1 and r0 are ignored. the bit 7 6 5 4 3 2 1 0 spmie rwwsb ? rwwsre blbset pgwrt pgers spmen spmcsr read/write r/w r r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 257 at90pwm216/316 [datasheet] 7710h?avr?07/2013 pgers bit will auto-clear upon co mpletion of a page erase, or if no spm in struction is executed within four clock cycles. the cpu is halted during the entire page write operation if the nrw w section is addressed. ? bit 0 ? spmen: self programming enable this bit enables the spm instruction for the next four clo ck cycles. if written to one together with either rwwsre, blbset, pgwrt or pgers, the followi ng spm instruction will have a special meaning, see description above. if only spmen is written, the following spm instruction will store the value in r1:r0 in the temporary page buffer addressed by the z-poin ter. the lsb of the z-pointer is ignored. the spmen bit will au to-clear upon completion of an spm instruction, or if no spm instruction is executed within four clock cycles. during page erase and page write, the spmen bit remains high until the operation is completed. writing any other combination than ?10 001?, ?01001?, ?00101?, ?00011? or ?00001? in the lowe r five bits will have no effect. 23.6 addressing the flash during self-programming the z-pointer is used to address the spm commands. since the flash is organized in pages (see table 24-11 on page 270 ), the program counter can be treated as hav- ing two different sections. one section, consisting of t he least significant bits, is addressing the words within a page, while the most significant bits ar e addressing the pages. this is1 shown in figure 23-3 . note that the page erase and page write operations are addressed independently . therefore it is of major importance that the boot loader software addresses the same page in both the page erase and page write operation. once a program- ming operation is initiated, the ad dress is latched and the z-pointer can be used for other operations. the only spm operation that does not use the z-pointer is setting the boot loader lock bits. the content of the z- pointer is ignored and will have no effect on the operation. the lpm instruction does also use the z-pointer to store the address. since this instruction addres ses the flash byte-by-byte, also the lsb (bit z0) of the z-pointer is used. bit 151413121110 9 8 zh (r31) z15 z14 z13 z12 z11 z10 z9 z8 zl (r30) z7z6z5z4z3z2z1z0 76543210 258 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 23-3. addressing the flash during spm (1) note: 1. the different variables used in figure 23-3 are listed in table 23-8 on page 263 . 23.7 self-programming the flash the program memory is updated in a page by page fashio n. before programming a page with the data stored in the temporary page buffer, t he page must be erased . the temporary pa ge buffer is filled one wo rd at a time using spm and the buffer can be filled either bef ore the page erase command or between a page erase and a page write operation: alternative 1, fill the bu ffer before a page erase ? fill temporary page buffer ? perform a page erase ? perform a page write alternative 2, fill the buffer after page erase ? perform a page erase ? fill temporary page buffer ? perform a page write if only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary page buffer) before the erase, and then be rewritten. w hen using alternative 1, the boot loader provides an effec- tive read-modify-write feature which allows the user so ftware to first read the page, do the necessary changes, and then write back the modified data. if alternative 2 is used, it is not pos sible to read the old data while loading since the page is already erased. the temporary page buffer can be accessed in a random sequence. it is essen- tial that the page address used in both the page eras e and page write operation is addressing the same page. see ?simple assembly code example for a boot loader? on page 261 for an assembly code example. program memory 0 1 15 z - register bit 0 zpagemsb word address within a page page address within the flash zpcmsb instruction word pag e pcword[pagemsb:0]: 00 01 02 pageend pag e pcword pcpage pcmsb pagemsb program counter 259 at90pwm216/316 [datasheet] 7710h?avr?07/2013 23.7.1 performing page erase by spm to execute page erase, set up the address in the z-pointer, write ?x0000011? to spmcsr and execute spm within four clock cycles after writing spmcsr. the data in r1 and r0 is ignored. the page address must be writ- ten to pcpage in the z-register . other bits in the z-pointer will be ignored during this operation. ? page erase to the rww section: the nrww section can be read during the page erase. ? page erase to the nrww section: the cpu is halted during the operation. 23.7.2 filling the temporary buffer (page loading) to write an instructio n word, set up the address in the z-pointer and data in r1:r0, write ?00000001? to spmcsr and execute spm within four clock cycles after writing sp mcsr. the content of pcword in the z-register is used to address the data in the temporary buffer. the temporar y buffer will auto-era se after a page write operation or by writing the rwwsre bit in spmcsr. it is also erased afte r a system reset. note that it is not possible to write more than one time to each address without erasing the temporary buffer. if the eeprom is written in the middle of an spm page load operation, all dat a loaded will be lost. 23.7.3 performing a page write to execute page write, set up the address in the z-po inter, write ?x0000101? to spmcsr and execute spm within four clock cycles after writing spmcsr. the data in r1 an d r0 is ignored. the page address must be written to pcpage. other bits in the z-pointer must be written to zero du ring this operation. ? page write to the rww section: the nrww section can be read during the page write. ? page write to the nrww section: the cpu is halted during the operation. 23.7.4 using the spm interrupt if the spm interrupt is enabled, the spm interrupt will generate a constant interrupt when the spmen bit in spmcsr is cleared. this means that the interrupt can be used instead of polling the spmcsr register in soft- ware. when using the spm interrupt, the interrupt vector s should be moved to the bls section to avoid that an interrupt is accessing the rww section when it is blocked for reading. how to move the interrupts is described in xxxxxxxx. 23.7.5 consideration while updating bls special care must be taken if the user allows the b oot loader section to be updated by leaving boot lock bit11 unprogrammed. an accidental write to the boot loader itself can corrupt the entire boot loader, and further soft- ware updates might be impossible. if it is not necessary to change the boot loader software itself, it is recommended to program the boot lock bit11 to protect the boot loader so ftware from any internal software changes. 23.7.6 prevent reading the rww section during self-programming during self-programming (either page erase or page writ e), the rww section is always blocked for reading. the user software itself must prevent that this section is addressed during the self programming operation. the rwwsb in the spmcsr will be set as long as the rww section is busy. during self-programming the interrupt vector table should be moved to the bls as described in xxxxxxx, or the interrupts must be disabled. before addressing the rww section after the programming is co mpleted, the user software must clear the rwwsb by writing the rwwsre. see ?simple assembly code example for a boot loader? on page 261 for an example. 260 at90pwm216/316 [datasheet] 7710h?avr?07/2013 23.7.7 setting the boot loader lock bits by spm to set the boot loader lock bits, write the desired data to r0, write ?x0001001? to spmcsr and execute spm within four clock cycles after writing spmcsr. the only ac cessible lock bits are the b oot lock bits that may pre- vent the application and boot loader sectio n from any software update by the mcu. see table 23-2 and table 23-3 for how the different settings of the boot loader bits affect the flash access. if bits 5..2 in r0 are cleared (zero), the corresponding boot lock bit will be programmed if an spm instruction is executed within four cycles after blbset and spmen are set in spmcsr. the z-pointe r is don?t care during this operation, but for future compatibility it is recommended to load the z-pointer with 0x 0001 (same as used for read- ing the lo ck bits). for future compatibility it is also recommended to set bits 7, 6, 1, and 0 in r0 to ?1? when writing the lock bits. when programming the lock bits the entire flash can be read during the operation. 23.7.8 eeprom write prevents writing to spmcsr note that an eeprom write operation will block all software programming to flash. reading the fuses and lock bits from software will also be prevented during the e eprom write operati on. it is recomm ended that the user checks the status bit (eepe) in the eecr register and verifies th at the bit is cleared bef ore writing to the spmcsr register. 23.7.9 reading the fuse and lock bits from software it is possible to read both the fuse and lock bits from software. to read the lock bits, load the z-pointer with 0x0001 and set the blbset and spmen bits in spmcsr. wh en an lpm instruction is executed within three cpu cycles after the bl bset and spmen bits are set in spmcsr, the value of the lock bi ts will be loaded in the des- tination register. the blbset and spmen bits will auto-clear upon completion of reading the lock bits or if no lpm instruction is executed within three cpu cycles or no spm instruction is executed within four cpu cycles. when blbset and spmen are cleared, lpm will work as described in the in struction set manual. the algorithm for reading the fuse low byte is similar to the one described above for reading the lock bits. to read the fuse low byte, load the z- pointer with 0x0000 and se t the blbset and spmen bits in spmcsr. when an lpm instruction is executed within three cycles afte r the blbset and spmen bits are set in the spmcsr, the value of the fuse low byte (flb) will be loaded in the de stination register as shown below. refer to table 24-4 on page 266 for a detailed description and mapping of the fuse low byte. similarly, when reading the fuse high byte, load 0x0003 in the z-pointer. when an lpm instruction is executed within three cycles after the blbset and spmen bits ar e set in the spmcsr, the va lue of the fuse high byte (fhb) will be loaded in the destination register as shown below. refer to table 24-5 on page 267 for detailed description and mapping of the fuse high byte. when reading the extended fuse byte, load 0x0002 in the z-pointer. when an lpm instruction is executed within three cycles after the blbset and spmen bits are set in the spmcsr, the value of the extended fuse byte bit 76543210 r0 1 1 blb12 blb11 blb02 blb01 1 1 bit 76543210 rd ? ? blb12 blb11 blb02 blb01 lb2 lb1 bit 76543210 rd flb7 flb6 flb5 flb4 flb3 flb2 flb1 flb0 bit 76543210 rd fhb7 fhb6 fhb5 fhb4 fhb3 fhb2 fhb1 fhb0 261 at90pwm216/316 [datasheet] 7710h?avr?07/2013 (efb) will be loaded in the destinatio n register as shown below. refer to table 24-4 on page 266 for detailed description and mapping of the extended fuse byte. fuse and lock bits that are progra mmed, will be read as zero . fuse and lock bits that are unprogrammed, will be read as one. 23.7.10 preventing flash corruption during periods of low v cc , the flash program can be corrupted because the supply voltage is too low for the cpu and the flash to operate properly. these issues are the sa me as for board level systems using the flash, and the same design solutions should be applied. a flash program corruption can be caused by two situations when the voltage is too low. first, a regular write sequence to the flash requires a minimum voltage to operate correctly. secondly, the cpu itself can execute instructions incorrectly, if the supply vo ltage for executing inst ructions is too low. flash corruption can easily be avoided by following these design recommendations (one is sufficient): 1. if there is no need for a boot loader update in the system, program the boot loader lock bits to prevent any boot loader software updates. 2. keep the avr reset active (low) during periods of in sufficient power supply vo ltage. this can be done by enabling the internal brown-out detector (bod) if the operating voltage matches the detection level. if not, an external low v cc reset protection circuit can be used. if a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 3. keep the avr core in power-down sleep mode during periods of low v cc . this will prevent the cpu from attempting to decode and execute inst ructions, effectively protecting th e spmcsr register and thus the flash from unintentional writes. 23.7.11 programming time for flash when using spm the calibrated rc oscillator is used to time flash accesses. table 23-5 shows the typical programming time for flash accesses from the cpu. 23.7.12 simple assembly code example for a boot loader ;-the routine writes one page of data from ram to flash ; the first data location in ram is pointed to by the y pointer ; the first data location in flash is pointed to by the z-pointer ;-error handling is not included ;-the routine must be placed inside the boot space ; (at least the do_spm sub routine). only code inside nrww section can ; be read during self-programming (page erase and page write). ;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24), ; loophi (r25), spmcrval (r20) ; storing and restoring of registers is not included in the routine ; register usage can be optimized at the expense of code size ;-it is assumed that either the interrupt table is moved to the boot ; loader section or that the interrupts are disabled. .equ pagesizeb = pagesize*2 ;pagesizeb is page size in bytes, not words .org smallbootstart write_page: bit 76543210 rd ? ? ? ? efb3 efb2 efb1 efb0 table 23-5. spm programming time symbol min programming time max programming time flash write (page eras e, page write, and write lock bits by spm) 3.7 ms 4.5 ms 262 at90pwm216/316 [datasheet] 7710h?avr?07/2013 ; page erase ldi spmcrval, (1< 264 at90pwm216/316 [datasheet] 7710h?avr?07/2013 note: 1. z15:z14: always ignored z0: should be zero for all spm commands, byte select for the lpm instruction. see ?addressing the flash during self-programming? on page 257 for details about the use of z-pointer during self-programming. pagemsb 5 most significant bit which is used to address the words within one page (32 words in a page requires 5 bits pc [4:0]). zpcmsb z13 bit in z-register that is mapped to pcmsb. because z0 is not used, the zpcmsb equals pcmsb + 1. zpagemsb z6 bit in z-register that is mapped to pagemsb. because z0 is not used, the zpagemsb equals pagemsb + 1. pcpage pc[12:6] z13:z7 program counter page address: page select, for page erase and page write pcword pc[5:0] z6:z1 program counter word add ress: word select, for filling temporary buffer (must be zero during page write operation) table 23-8. explanation of different variables used in figure 23-3 and the mapping to the z-pointer variable corresponding z-value (1) description 265 at90pwm216/316 [datasheet] 7710h?avr?07/2013 24. memory programming 24.1 program and data memory lock bits the at90pwm216/316 provides six lock bits which can be left unprogrammed (?1?) or can be programmed (?0?) to obtain the additional features listed in table 24-2 . the lock bits can only be eras ed to ?1? with the chip erase command. notes: 1. ?1? means unprogrammed, ?0? means programmed. notes: 1. program the fuse bits and boot lock bits before programming the lb1 and lb2. 2. ?1? means unprogrammed, ?0? means programmed table 24-1. lock bit byte (1) lock bit byte bit no description default value 7 ? 1 (unprogrammed) 6 ? 1 (unprogrammed) blb12 5 boot lock bit 1 (unprogrammed) blb11 4 boot lock bit 1 (unprogrammed) blb02 3 boot lock bit 1 (unprogrammed) blb01 2 boot lock bit 1 (unprogrammed) lb2 1 lock bit 1 (unprogrammed) lb1 0 lock bit 1 (unprogrammed) table 24-2. lock bit protection modes (1)(2) memory lock bits protection type lb mode lb2 lb1 1 1 1 no memory lock features enabled. 210 further programming of the fl ash and eeprom is disabled in parallel and serial programming mode. the fuse bits are locked in both serial and parallel programming mode. (1) 300 further programming and verification of the flash and eeprom is disabled in parallel and serial programming mode. the boot lock bits and fuse bits are locked in both serial and parallel programming mode. (1) table 24-3. lock bit protection modes (1)(2) . blb0 mode blb02 blb01 1 1 1 no restrictions for spm or lpm accessing the application section. 2 1 0 spm is not allowed to write to the application section. 300 spm is not allowed to write to the applic ation section, and lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. 401 lpm executing from the boot loader sect ion is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while execut ing from the application section. 266 at90pwm216/316 [datasheet] 7710h?avr?07/2013 notes: 1. program the fuse bits and boot lock bits before programming the lb1 and lb2. 2. ?1? means unprogrammed, ?0? means programmed 24.2 fuse bits the at90pwm216/316 has three fuse bytes. table 24-4 - table 24-6 describe briefly the functionality of all the fuses and how they are mapped into the fuse bytes. note that the fuses are read as logical zero, ?0?, if they are programmed. note: 1. the default value of bootsz1..0 results in maximum boot size. see table 24-7 on page 269 for details. 24.3 psc output be havior during reset for external component safety reason, the state of psc outputs during reset can be programmed by fuses pscrv, psc0rb, psc1rb & psc2rb. these fuses are located in the extended fuse byte (see table 24-4 ). pscrv gives the state low or high which will be forced on psc outputs selected by psc0rb, psc1rb & psc2rb fuses. if pscrv fuse equals 0 (programmed), the selected ps c outputs will be forced to high state. if pscrv fuse equals 1 (unprogra mmed), the selected psc output s will be forced to low state. if psc0rb fuse equals 1 (unprogrammed), pscout00 & pscout01 keep a standard port behaviour. if psc0rb fuse equals 0 (programmed), pscout00 & pscout01 are forc ed at reset to low level or high level according to blb1 mode blb12 blb11 1 1 1 no restrictions for spm or lpm accessing the boot loader section. 2 1 0 spm is not allowed to write to the boot loader section. 300 spm is not allowed to write to the boot loader section, and lpm executing from the application section is not allowed to read fr om the boot loader section. if interrupt vectors are placed in the application secti on, interrupts are disabled while executing from the boot loader section. 401 lpm executing from the applic ation section is not allowed to read from the boot loader section. if interrupt vectors are pl aced in the application section, interrupts are disabled while executing fr om the boot loader section. table 24-3. lock bit protection modes (1)(2) . table 24-4. extended fuse byte extended fuse byte bit no description default value psc2rb 7 psc2 reset behaviour 1 psc1rb 6 psc1 reset behaviour 1 psc0rb 5 psc0 reset behaviour 1 pscrv 4 pscout reset value 1 ?3? 1 bootsz1 2 select boot size (see table 113 for details) 0 (programmed) (1) bootsz0 1 select boot size (see table 113 for details) 0 (programmed) (1) bootrst 0 select reset vector 1 (unprogrammed) 267 at90pwm216/316 [datasheet] 7710h?avr?07/2013 pscrv fuse bit. in this second ca se, pscout00 & pscout01 keep the forced state until psoc0 register is written.. if psc1rb fuse equals 1 (unprogrammed), pscout10 & pscout11 keep a standard port behavior. if psc1rb fuse equals 0 (programmed), pscout10 & pscout11 are forc ed at reset to low level or high level according to pscrv fuse bit. in this second ca se, pscout10 & pscout11 keep the forced state until psoc1 register is written. if psc2rb fuse equals 1 (unprogrammed), pscout 20, pscout21, pscout22 & pscout23 keep a standard port behavior. if psc1rb fuse equals 0 (programm ed), pscout20, pscout21, pscout22 & pscout23 are forced at reset to low level or high level accordi ng to pscrv fuse bit. in this second case, pscout20, pscout21, pscout22 & pscout23 keep the forced state until psoc2 register is written. notes: 1. see ?alternate functions of port c? on page 65 for description of rstdisbl fuse. 2. the spien fuse is not accessible in serial programming mode. 3. see ?watchdog timer configuration? on page 49 for details. 4. see table 8-2 on page 42 for bodlevel fuse decoding. note: 1. the default value of sut1..0 results in maximu m start-up time for the default clock source. see table 6-9 on page 32 for details. 2. the default setting of cksel3..0 results in internal rc oscillator @ 8 mhz. see table 6-9 on page 32 for details. 3. the ckout fuse allows the system clock to be output on portb0. see ?clock output buffer? on page 32 for details. 4. see ?system clock prescaler? on page 32 for details. table 24-5. fuse high byte high fuse byte bit no description default value rstdisbl (1) 7 external reset disable 1 (unprogrammed) dwen 6 debugwire enable 1 (unprogrammed) spien (2) 5 enable serial program and data downloading 0 (programmed, spi programming enabled) wdton (3) 4 watchdog timer always on 1 (unprogrammed) eesave 3 eeprom memory is preserved through the chip erase 1 (unprogrammed), eeprom not reserved bodlevel2 (4) 2 brown-out detector trigger level 1 (unprogrammed) bodlevel1 (4) 1 brown-out detector trigger level 1 (unprogrammed) bodlevel0 (4) 0 brown-out detector trigger level 1 (unprogrammed) table 24-6. fuse low byte low fuse byte bit no description default value ckdiv8 (4) 7 divide clock by 8 0 (programmed) ckout (3) 6 clock output 1 (unprogrammed) sut1 5 select start-up time 1 (unprogrammed) (1) sut0 4 select start-up time 0 (programmed) (1) cksel3 3 select clock source 0 (programmed) (2) cksel2 2 select clock source 0 (programmed) (2) cksel1 1 select clock source 1 (unprogrammed) (2) cksel0 0 select clock source 0 (programmed) (2) 268 at90pwm216/316 [datasheet] 7710h?avr?07/2013 the status of the fuse bits is not affected by chip erase. note that the fuse bits are locked if lock bit1 (lb1) is programmed. program the fuse bits before programming the lock bits. 24.3.1 latching of fuses the fuse values are latched when the device enters pr ogramming mode and changes of the fuse values will have no effect until the part le aves programming mode. this does not apply to the eesave fuse which will take effect once it is programmed. the fuses are also latched on power-up in normal mode. 24.4 signature bytes all atmel microcontrollers have a three-byte signature c ode which identifies the device. this code can be read in both serial and parallel mode, also when the device is lo cked. the three bytes reside in a separate address space. 24.4.1 signature bytes for the at90pwm216/316 the signature bytes are: 1. 0x000: 0x1e (indicates manufactured by atmel). 2. 0x001: 0x94 (indicates 16kb flash memory). 3. 0x002: 0x83 (indicates aat90pwm 216/316 device when 0x001 is 0x94). 24.5 calibration byte the at90pwm216/316 has a byte calibration value for the internal rc oscilla tor. this byte resides in the high byte of address 0x000 in the signature address space. during re set, this byte is automati cally written into the osccal register to ensure correct frequen cy of the calibrated rc oscillator. 24.6 parallel programming paramete rs, pin mapping, and commands this section describes how to parallel program and ve rify flash program memory , eeprom data memory, mem- ory lock bits, and fuse bits in the at90pwm216/316. puls es are assumed to be at least 250 ns unless otherwise noted. 24.6.1 signal names in this section, some pins of the at90pwm216/316 are referenced by signal names describing their functionality during parallel programming, see figure 24-1 and table 24-7 . pins not described in the following table are refer- enced by pin names. the xa1/xa0 pins determine the action executed when the xtal1 pin is giv en a positive pulse. the bit coding is shown in table 24-9 . when pulsing wr or oe , the command loaded determines the action executed. the different commands are shown in table 24-10 . 269 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 24-1. parallel programming table 24-7. pin name mapping signal name in programming mode pin name i/o function rdy/bsy pd1 o 0: device is busy programming, 1: device is ready for new command oe pd2 i output enable (active low) wr pd3 i write pulse (active low) bs1 pd4 i byte select 1 (?0? select s low byte, ?1? selects high byte) xa0 pd5 i xtal action bit 0 xa1 pd6 i xtal action bit 1 pagel pd7 i program memory and eeprom data page load bs2 pe2 i byte select 2 (?0? selects low byte, ?1? selects 2?nd high byte) data pb[7:0] i/o bi-directional data bus (output when oe is low) table 24-8. pin values used to enter programming mode pin symbol value pagel prog_enable[3] 0 xa1 prog_enable[2] 0 xa0 prog_enable[1] 0 bs1 prog_enable[0] 0 v cc g n d xtal1 xa0 rdy/bsy oe reset + 5 v a v cc + 5 v pd1 + 12 v pd7 pd6 pd5 pd4 pd3 pd2 pe2 wr xa1 bs2 pagel bs1 data pb[7:0] 270 at90pwm216/316 [datasheet] 7710h?avr?07/2013 24.7 serial programming pin mapping table 24-9. xa1 and xa0 coding xa1 xa0 action when xtal1 is pulsed 0 0 load flash or eeprom address (high or low address byte determined by bs1). 0 1 load data (high or low data byte for flash determined by bs1). 1 0 load command 1 1 no action, idle table 24-10. command byte bit coding command byte command executed 1000 0000 chip erase 0100 0000 write fuse bits 0010 0000 write lock bits 0001 0000 write flash 0001 0001 write eeprom 0000 1000 read signature bytes and calibration byte 0000 0100 read fuse and lock bits 0000 0010 read flash 0000 0011 read eeprom table 24-11. no. of words in a page and no. of pages in the flash device flash size page size pcword no. of pages pcpage pcmsb at90pwm216/316 8k words (16k bytes) 64 words pc[5:0] 128 pc[12:6] 12 table 24-12. no. of words in a page and no. of pages in the eeprom device eeprom size page size pcword no. of pages pcpage eeamsb at90pwm216/316 512 bytes 4 bytes eea[1:0] 128 eea[8:2] 8 table 24-13. pin mapping serial programming symbol pins i/o description mosi_a pd3 i serial data in miso_a pd2 o serial data out sck_a pd4 i serial clock 271 at90pwm216/316 [datasheet] 7710h?avr?07/2013 24.8 parallel programming 24.8.1 enter programming mode the following algorithm puts the device in parallel (high-voltage) > programming mode: 1. set prog_enable pins listed in table 24-8. to ?0000?, reset pin to ?0? and vcc to 0v. 2. apply 4.5 - 5.5v between vcc and gnd. ensure that vcc reaches at least 1.8v within the next 20s. 3. wait 20 - 60s, and apply 11.5 - 12.5v to reset. 4. keep the prog_enable pins unchanged for at least 10s after the high-voltage has been applied to ensure the prog_enable signature has been latched. 5. wait at least 300s before giving any parallel programming commands. 6. exit programming mode by po wer the device down or by bringing reset pin to 0v. if the rise time of the vcc is unable to fulfill t he requirements listed abo ve, the following alternative algorithm can be used. 1. set prog_enable pins listed in table 24-8. to ?0000?, reset pin to ?0? and vcc to 0v. 2. apply 4.5 - 5.5v between vcc and gnd. 3. monitor vcc, and as soon as vcc reaches 0.9 - 1.1v, app ly 11.5 - 12.5v to reset. 4. keep the prog_enable pins unchanged for at least 10s after the high-voltage has been applied to ensure the prog_enable signature has been latched. 5. wait until vcc actually reaches 4.5 -5.5v be fore giving any parallel programming commands. 6. exit programming mode by po wer the device down or by bringing reset pin to 0v. 24.8.2 considerations for efficient programming the loaded command and address are retained in the devic e during programming. for efficient programming, the following should be considered. ? the command needs only be loaded once when writing or reading multiple memory locations. ? skip writing the data value 0xff, that is the cont ents of the entire eeprom (u nless the eesave fuse is programmed) and flash after a chip erase. ? address high byte needs only be loaded before programming or reading a new 256 word window in flash or 256 byte eeprom. this consideration al so applies to signature bytes reading. 24.8.3 chip erase the chip erase will erase the flash and eeprom (1) memories plus lock bits. the lo ck bits are not reset until the program memory has been completely erased. the fuse bits are not changed. a chip erase must be performed before the flas h and/or eeprom are reprogrammed. note: 1. the eeprpom memory is preserved during ch ip erase if the eesave fuse is programmed. load command ?chip erase? 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?1000 0000?. this is the command for chip erase. 4. give xtal1 a positive pulse. this loads the command. 5. give wr a negative pulse. this st arts the chip erase. rdy/bsy goes low. 6. wait until rdy/bsy goes high before loading a new command. 272 at90pwm216/316 [datasheet] 7710h?avr?07/2013 24.8.4 programming the flash the flash is organized in pages, see table 24-11 on page 270 . when programming the flash, the program data is latched into a page buffer. this allows one page of prog ram data to be programmed simultaneously. the following procedure describes how to program the entire flash memory: a. load command ?write flash? 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?0001 0000?. this is the command for write flash. 4. give xtal1 a positive pulse. this loads the command. b. load address low byte 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs1 to ?0?. this selects low address. 3. set data = address low byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the address low byte. c. load data low byte 1. set xa1, xa0 to ?01?. this enables data loading. 2. set data = data low byte (0x00 - 0xff). 3. give xtal1 a positive pulse. this loads the data byte. d. load data high byte 1. set bs1 to ?1?. this selects high data byte. 2. set xa1, xa0 to ?01?. this enables data loading. 3. set data = data high byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the data byte. e. latch data 1. set bs1 to ?1?. this selects high data byte. 2. give pagel a positive pulse. this latches the data bytes. (see figure 24-3 for signal waveforms) f. repeat b through e until the entire buffer is filled or until all data within the page is loaded. while the lower bits in the address are mapped to words within the page, the higher bits address the pages within the flash. this is illustrated in figure 24-2 on page 273 . note that if less than eight bits are required to address words in the page (page size < 256), the most significant bit(s) in the address low byte are used to address the page when performing a page write. g. load address high byte 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs1 to ?1?. this selects high address. 3. set data = address high byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the address high byte. h. program page 1. give wr a negative pulse. this starts programming of the entire page of data. rdy/bsy goes low. 2. wait until rdy/bsy goes high (see figure 24-3 for signal waveforms). i. repeat b through h until the entire flash is programmed or until all data has been programmed. j. end page programming 273 at90pwm216/316 [datasheet] 7710h?avr?07/2013 1. 1. set xa1, xa0 to ?10?. this enables command loading. 2. set data to ?0000 0000?. this is the command for no operation. 3. give xtal1 a positive pulse. this loads the command, and the internal write signals are reset. figure 24-2. addressing the flash which is organized in pages (1) note: 1. pcpage and pcword are listed in table 24-11 on page 270 . figure 24-3. programming the flash waveforms (1) note: 1. ?xx? is don?t care. the letters refer to the programming description above. 24.8.5 programming the eeprom the eeprom is organized in pages, see table 24-12 on page 270 . when programming the eeprom, the pro- gram data is latched into a page buffer. this allows one page of data to be programmed simultaneously. the programming algorithm for the eeprom data memory is as follows (refer to ?programming the flash? on page 272 for details on command, address and data loading): 1. a: load command ?0001 0001?. 2. g: load address high byte (0x00 - 0xff). program memory word address within a page page address within the flash instruction word pag e pcword[pagemsb:0]: 00 01 02 pageend pag e pcword pcpage pcmsb pagemsb program counter rdy/bsy wr oe reset +12v pagel bs2 0x10 addr. low addr. high data data low data high addr. low data low data high xa1 xa0 bs1 xtal1 xx xx xx abcdeb cdegh f 274 at90pwm216/316 [datasheet] 7710h?avr?07/2013 3. b: load address low byte (0x00 - 0xff). 4. c: load data (0x00 - 0xff). 5. e: latch data (give pagel a positive pulse). k: repeat 3 through 5 until the entire buffer is filled. l: program eeprom page 1. set bs1 to ?0?. 2. give wr a negative pulse. this starts pr ogramming of the eeprom page. rdy/bsy goes low. 3. wait until to rdy/bsy goes high before programming the next page (see figure 24-4 for signal waveforms). figure 24-4. programming the eeprom waveforms 24.8.6 reading the flash the algorithm for reading the flash memory is as follows (refer to ?programming the flash? on page 272 for details on command and address loading): 1. a: load command ?0000 0010?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. set oe to ?0?, and bs1 to ?0?. the flash word low byte can now be read at data. 5. set bs1 to ?1?. the flash word high byte can now be read at data. 6. set oe to ?1?. 24.8.7 reading the eeprom the algorithm for reading the eeprom memory is as follows (refer to ?programming the flash? on page 272 for details on command and address loading): 1. a: load command ?0000 0011?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. set oe to ?0?, and bs1 to ?0?. the eeprom data byte can now be read at data. 5. set oe to ?1?. rdy/bsy wr oe reset +12v pagel bs2 0x11 addr. high data addr. low data addr. low data xx xa1 xa0 bs1 xtal1 xx agbceb c el k 275 at90pwm216/316 [datasheet] 7710h?avr?07/2013 24.8.8 programming the fuse low bits the algorithm for programming the fuse low bits is as follows (refer to ?programming the flash? on page 272 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. give wr a negative pulse and wait for rdy/bsy to go high. 24.8.9 programming the fuse high bits the algorithm for programming the fuse high bits is as follows (refer to ?programming the flash? on page 272 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. set bs1 to ?1? and bs2 to ?0?. this selects high data byte. 4. give wr a negative pulse and wait for rdy/bsy to go high. 5. set bs1 to ?0?. this selects low data byte. 24.8.10 programming the extended fuse bits the algorithm for programming the extended fuse bits is as follows (refer to ?programming the flash? on page 272 for details on command and data loading): 1. 1. a: load command ?0100 0000?. 2. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. 3. set bs1 to ?0? and bs2 to ?1?. this selects extended data byte. 4. 4. give wr a negative pulse and wait for rdy/bsy to go high. 5. 5. set bs2 to ?0?. this selects low data byte. figure 24-5. programming the fuses waveforms 24.8.11 programming the lock bits the algorithm for programming the lock bits is as follows (refer to ?programming the flash? on page 272 for details on command and data loading): rdy/bsy wr oe reset +12v pagel 0x40 data data xx xa1 xa0 bs1 xtal1 ac 0x40 data xx ac write fuse low byte write fuse high byte 0x40 data xx ac write extended fuse byte bs2 276 at90pwm216/316 [datasheet] 7710h?avr?07/2013 1. a: load command ?0010 0000?. 2. c: load data low byte. bit n = ?0? programs the lock bit. if lb mode 3 is programmed (lb1 and lb2 is programmed), it is not possible to program the b oot lock bits by any external programming mode. 3. give wr a negative pulse and wait for rdy/bsy to go high. the lock bits can only be cleared by executing chip erase. 24.8.12 reading the fuse and lock bits the algorithm for reading the fuse and lock bits is as follows (refer to ?programming the flash? on page 272 for details on command loading): 1. a: load command ?0000 0100?. 2. set oe to ?0?, bs2 to ?0? and bs1 to ?0?. the status of the fuse low bits can now be read at data (?0? means programmed). 3. set oe to ?0?, bs2 to ?1? and bs1 to ?1?. the status of the fuse high bits can now be read at data (?0? means programmed). 4. set oe to ?0?, bs2 to ?1?, and bs1 to ?0?. the stat us of the extended fuse bits can now be read at data (?0? means programmed). 5. set oe to ?0?, bs2 to ?0? and bs1 to ?1?. the status of the lock bits can now be read at data (?0? means programmed). 6. set oe to ?1?. figure 24-6. mapping between bs1, bs2 and the fuse and lock bits during read 24.8.13 reading the signature bytes the algorithm for reading the signature bytes is as follows (refer to ?programming the flash? on page 272 for details on command and address loading): 1. a: load command ?0000 1000?. 2. b: load address low byte (0x00 - 0x02). 3. set oe to ?0?, and bs1 to ?0?. the selected signature byte can now be read at data. 4. set oe to ?1?. 24.8.14 reading the calibration byte the algorithm for reading the calibration byte is as follows (refer to ?programming the flash? on page 272 for details on command and address loading): lock bits 0 1 bs2 fuse high byte 0 1 bs1 data fuse low byte 0 1 bs2 extended fuse byte 277 at90pwm216/316 [datasheet] 7710h?avr?07/2013 1. a: load command ?0000 1000?. 2. b: load address low byte, 0x00. 3. set oe to ?0?, and bs1 to ?1?. the calibration byte can now be read at data. 4. set oe to ?1?. 24.8.15 parallel programming characteristics figure 24-7. parallel programming timing, including some general timing requirements figure 24-8. parallel programming timing, loading sequence with timing requirements (1) note: 1. the timing requirements shown in figure 24-7 (i.e., t dvxh , t xhxl , and t xldx ) also apply to loading operation. data & contol (data, xa0/1, bs1, bs2) xtal1 t xhxl t wlwh t dvxh t xldx t plwl t wlrh wr rdy/bsy pagel t phpl t plbx t bvph t xlwl t wlbx t bvwl wlrl xtal1 pagel t plxh xlxh t t xlph addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data bs1 xa0 xa1 load address (low byte) load data (low byte) load data (high byte) load data load address (low byte) 278 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 24-9. parallel programming timing, reading sequence (within the same page) with timing requirements (1) note: 1. the timing requirements shown in figure 24-7 (i.e., t dvxh , t xhxl , and t xldx ) also apply to reading operation. table 24-14. parallel programming characteristics, v cc = 5v 10% symbol parameter min typ max units v pp programming enable voltage 11.5 12.5 v i pp programming enable current 250 ? a t dvxh data and control valid before xtal1 high 67 ns t xlxh xtal1 low to xtal1 high 200 ns t xhxl xtal1 pulse width high 150 ns t xldx data and control hold after xtal1 low 67 ns t xlwl xtal1 low to wr low 0 ns t xlph xtal1 low to pagel high 0 ns t plxh pagel low to xtal1 high 150 ns t bvph bs1 valid before pagel high 67 ns t phpl pagel pulse width high 150 ns t plbx bs1 hold after pagel low 67 ns t wlbx bs2/1 hold after wr low 67 ns t plwl pagel low to wr low 67 ns t bvwl bs1 valid to wr low 67 ns t wlwh wr pulse width low 150 ns t wlrl wr low to rdy/bsy low 0 1 ? s t wlrh wr low to rdy/bsy high (1) 3.7 4.5 ms t wlrh_ce wr low to rdy/bsy high for chip erase (2) 7.5 9 ms t xlol xtal1 low to oe low 0 ns t bvdv bs1 valid to data valid 0 250 ns t oldv oe low to data valid 250 ns t ohdz oe high to data tri-stated 250 ns xtal1 oe addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data bs1 xa0 xa1 load address (low byte) read data (low byte) read data (high byte) load address (low byte) t bvdv t oldv t xlol t ohdz 279 at90pwm216/316 [datasheet] 7710h?avr?07/2013 notes: 1. t wlrh is valid for the write flash, write eeprom, wr ite fuse bits and write lock bits commands. 2. t wlrh_ce is valid for the chip erase command. 24.9 serial downloading both the flash and eeprom memory arrays can be programmed using the serial spi bus while reset is pulled to gnd. the serial interface consists of pins sck, mosi (input) and mi so (output) . after reset is set low, the programming enable instruction needs to be executed first before progra m/erase operations can be executed. note, in table 24-13 on page 270 , the pin mapping for spi programming is listed. not all pa rts use the spi pins dedicated for the inte rnal spi interface. figure 24-10. serial programming and verify (1) notes: 1. if the device is clocked by the internal oscillator, it is no need to connect a clock source to the xtal1 pin. 2. v cc - 0.3v < avcc < v cc + 0.3v, however, avcc should always be within 1.8 - 5.5v when programming the eeprom, an auto-erase cycle is bu ilt into the self-timed pr ogramming operation (in the serial mode only) and there is no need to first execut e the chip erase instruction. the chip erase operation turns the content of ever y memory location in both the progra m and eeprom arrays into 0xff. depending on cksel fuses, a valid cloc k must be present. the minimum low a nd high periods for the serial clock (sck) input are defined as follows: low: > 2 cpu clock cycles for f ck < 12 mhz, 3 cpu clock cycles for f ck >= 12 mhz high: > 2 cpu clock cycles for f ck < 12 mhz, 3 cpu clock cycles for f ck >= 12 mhz 24.9.1 serial programming algorithm when writing serial data to the at90pwm216/316, data is clocked on the rising edge of sck. when reading data from the at90 pwm216/316, data is clocked on the falling edge of sck. see figure 24-11 for timing details. to program and verify the at90pwm216/316 in the serial programming mode, the following sequence is recom- mended (see four byte instruction formats in table 24-16 ): 1. power-up sequence: apply power between v cc and gnd while reset and sck are set to ?0?. in some systems, the program- mer can not g uarantee that sck is he ld low during power-up. in this case, reset must be given a positive pulse of at least two cpu clock c ycles duration after sck has been set to ?0?. 2. wait for at least 20 ms and enable serial programmi ng by sending the programming enable serial instruc- tion to pin mosi. v cc g n d xtal1 sck_a miso_a mosi_a reset +1. 8 - 5.5 v a v cc +1. 8 - 5.5 v (2) 280 at90pwm216/316 [datasheet] 7710h?avr?07/2013 3. the serial programming instru ctions will not work if th e communication is out of synchronization. when in sync. the second byte (0x53), will echo back when issuing the third byte of the programming enable instruction. whether the echo is correc t or not, all four bytes of the inst ruction must be transmitted. if the 0x53 did not echo back, give reset a positive pulse and issue a new programming enable command. 4. the flash is programmed one page at a time. the memory page is loaded one byte at a time by supplying the 6 lsb of the address and data together with the load program memory page instruction. to ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. the program memory page is stored by loading the write program memory page instruction with the 8 msb of the address. if polling is not used, the us er must wait at least t wd_flash before issuing the next page. (see table 24-15 .) accessing the serial programming interface before the flash write operation completes can result in incorrect programming. 5. the eeprom array is programmed one byte at a time by supplying the address and data together with the appropriate write instruction. an eeprom memory location is first automatically erased before new data is written. if polling is not us ed, the user must wait at least t wd_eeprom before issuing the next byte. (see table 24-15 .) in a chip erased device, no 0xffs in the data file(s) need to be programmed. 6. any memory location can be verified by using th e read instruction which returns the content at the selected address at serial output miso. 7. at the end of the pr ogramming session, reset can be set high to commence normal operation. 8. power-off sequence (if needed): set reset to ?1?. turn v cc power off. 24.9.2 data polling flash when a page is being programmed into the flash, reading an address location within the page being programmed will give the value 0xff. at the time the device is ready for a new page, the program med value will read correctly. this is used to determine when the next page can be written. note that the entire page is written simultaneously and any address within th e page can be used for polling. data polling of the flash will not work for the value 0xff, so when programming this value, the us er will have to wait for at least t wd_flash before programming the next page. as a chip-erased device contains 0xff in all loca tions, programming of addresses that are meant to contain 0xff, can be skipped. see table 24-15 for t wd_flash value. 24.9.3 data polling eeprom when a new byte has been written an d is being programmed into eeprom, reading the addres s location being programmed will give the value 0xff. at the time the de vice is ready for a new byte, the programmed value will read correctly. this is used to determine when the next byte can be writ ten. this will not work for the value 0xff, but the user should have the following in mind: as a ch ip-erased device contains 0xff in all locations, program- ming of addresses that are meant to contain 0xff, can be skipped. this does not apply if the eeprom is re- programmed without chip erasing the device. in this ca se, data polling cannot be used for the value 0xff, and the user will have to wait at least t wd_eeprom before programming the next byte. see table 24-15 for t wd_eeprom value. table 24-15. minimum wait delay before writing the next flash or eeprom location symbol minimum wait delay t wd_flash 4.5 ms t wd_eeprom 3.6 ms t wd_erase 9.0 ms 281 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 24-11. serial programming waveforms msb msb lsb lsb serial clock input (sck) serial data input (mosi) (miso) sample serial data output table 24-16. serial programming instruction set instruction instruction format operation byte 1 byte 2 byte 3 byte4 programming enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx enable serial programming after reset goes low. chip erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx chip erase eeprom and flash. read program memory 0010 h 000 000 a aaaa bbbb bbbb oooo oooo read h (high or low) data o from program memory at word address a : b . load program memory page 0100 h 000 000x xxxx xx bb bbbb iiii iiii write h (high or low) data i to program memory page at word address b . data low byte must be loaded before data high byte is applied within the same address. write program memory page 0100 1100 000 a aaaa bb xx xxxx xxxx xxxx write program memory page at address a : b . read eeprom memory 1010 0000 000x xx aa bbbb bbbb oooo oooo read data o from eeprom memory at address a : b . write eeprom memory 1100 0000 000x xx aa bbbb bbbb iiii iiii write data i to eeprom memory at address a : b . load eeprom memory page (page access) 1100 0001 0000 0000 0000 00 bb iiii iiii load data i to eeprom memory page buffer. after data is loaded, program eeprom page. write eeprom memory page (page access) 1100 0010 00xx xx aa bbbb bb00 xxxx xxxx write eeprom page at address a : b . read lock bits 0101 1000 0000 0000 xxxx xxxx xx oo oooo read lock bits. ?0? = programmed, ?1? = unprogrammed. see table 24-1 on page 265 for details. write lock bits 1010 1100 111x xxxx xxxx xxxx 11 ii iiii write lock bits. set bits = ?0? to program lock bits. see table 24-1 on page 265 for details. read signature byte 0011 0000 000x xxxx xxxx xx bb oooo oooo read signature byte o at address b . write fuse bits 1010 1100 1010 0000 xxxx xxxx iiii iiii set bits = ?0? to program, ?1? to unprogram. see table xxx on page xxx for details. 282 at90pwm216/316 [datasheet] 7710h?avr?07/2013 note: a = address high bits, b = address low bits, h = 0 - low byte, 1 - high byte, o = data out, i = data in, x = don?t care 24.9.4 spi serial prog ramming characteristics for characteristics of the spi mo dule see ?spi serial programming characteristics? on page 282. write fuse high bits 1010 1100 1010 1000 xxxx xxxx iiii iiii set bits = ?0? to program, ?1? to unprogram. see table 24-5 on page 267 for details. write extended fuse bits 1010 1100 1010 0100 xxxx xxxx xxxx xxii set bits = ?0? to program, ?1? to unprogram. see table 24-4 on page 266 for details. read fuse bits 0101 0000 0000 0000 xxxx xxxx oooo oooo read fuse bits. ?0? = programmed, ?1? = unprogrammed. see table xxx on page xxx for details. read fuse high bits 0101 1000 0000 1000 xxxx xxxx oooo oooo read fuse high bits. ?0? = pro- grammed, ?1? = unprogrammed. see table 24-5 on page 267 for details. read extended fuse bits 0101 0000 0000 1000 xxxx xxxx oooo oooo read extended fuse bits. ?0? = pro- grammed, ?1? = unprogrammed. see table 24-4 on page 266 for details. read calibration byte 0011 1000 000x xxxx 0000 0000 oooo oooo read calibration byte poll rdy/bsy 1111 0000 0000 0000 xxxx xxxx xxxx xxx o if o = ?1?, a programming operation is still busy. wait until this bit returns to ?0? before applying another command. table 24-16. serial programming instruction set (continued) instruction instruction format operation byte 1 byte 2 byte 3 byte4 283 at90pwm216/316 [datasheet] 7710h?avr?07/2013 25. electrical characteristics 25.1 absolute maximum ratings* note: 1. electrical characteristics for this product have not ye t been finalized. please consid er all values listed herein as preliminary and non-contractual. operating temperature.................................. -40 ? c to +105 ? c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of th is specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65 ? c to +150 ? c voltage on any pin except reset with respect to ground ................................-0.5v to v cc +0.5v voltage on reset with respect to ground......-0.5v to +13.0v maximum operating voltage ............................................ 6.0v dc current per i/o pin ............................................... 40.0 ma dc current v cc and gnd pins................................ 200.0 ma 284 at90pwm216/316 [datasheet] 7710h?avr?07/2013 25.2 dc characteristics t a = -40 ? c to +105 ? c, v cc = 2.7v to 5.5v (unless otherwise noted) symbol parameter condition min. typ. max. units v il input low voltage port b, c & d and xtal1, xtal2 pins as i/o -0.5 0.2v cc (1) v v ih input high voltage port b, c & d and xtal1, xtal2 pins as i/o 0.6v cc (2) v cc +0.5 v v il1 input low voltage xtal1 pin, external clock selected -0.5 0.1v cc (1) v v ih1 input high voltage xtal1 pin, external clock selected 0.7v cc (2) v cc +0.5 v v il2 input low voltage reset pin -0.5 0.2v cc (1) v v ih2 input high voltage reset pin 0.9v cc (2) v cc +0.5 v v il3 input low voltage reset pin as i/o -0.5 0.2v cc (1) v v ih3 input high voltage reset pin as i/o 0.8v cc (2) v cc +0.5 v v ol output low voltage (3) (port b, c & d and xtal1, xtal2 pins as i/o) i ol = 20 ma, v cc = 5v i ol = 10 ma, v cc = 3v 0.7 0.5 v v v oh output high voltage (4) (port b, c & d and xtal1, xtal2 pins as i/o) i oh = -20 ma, v cc = 5v i oh = -10 ma, v cc = 3v 4.2 2.4 v v v ol3 output low voltage (3) (reset pin as i/o) i ol = 2.1 ma, v cc = 5v i ol = 0.8 ma, v cc = 3v 0.7 0.5 v v v oh3 output high voltage (4) (reset pin as i/o) i oh = -0.6 ma, v cc = 5v i oh = -0.4 ma, v cc = 3v 3.8 2.2 v v i il input leakage current i/o pin v cc = 5.5v, pin low (absolute value) 1a i ih input leakage current i/o pin v cc = 5.5v, pin high (absolute value) 1a r rst reset pull-up resistor 30 200 k ? r pu i/o pin pull-up resistor 20 50 k ? i cc power supply current active 8 mhz, v cc = 3v, rc osc, prr = 0xff 3.8 7 ma active 16 mhz, v cc = 5v, ext clock, prr = 0xff 14 24 ma idle 8 mhz, v cc = 3v, rc osc 1.5 3 ma idle 16 mhz, v cc = 5v, ext clock 5.5 10 ma power-down mode (5) wdt enabled, v cc = 3v t0 < 90c 515a wdt enabled, v cc = 3v t0 < 105c 920a wdt disabled, v cc = 3v t0 < 90c 1.5 3 a wdt disabled, v cc = 3v t0 < 105c 510a v acio analog comparator input offset voltage v cc = 5v, v in = 3v 20 50 mv 285 at90pwm216/316 [datasheet] 7710h?avr?07/2013 note: 1. ?max? means the highest value where the pin is guaranteed to be read as low 2. ?min? means the lowest value where th e pin is guaranteed to be read as high 3. although each i/o port can sink more than the test conditions (20 ma at v cc = 5v, 10 ma at v cc = 3v) under steady state conditions (non-transient), t he following must be observed: so32, so24 and tqfn package: 1] the sum of all iol, for all ports, should not exceed 400 ma. 2] the sum of all iol, for ports b6 - b7, c0 - c1, d0 - d3, e0 should not exceed 100 ma. 3] the sum of all iol, for ports b0 - b1, c2 - c3, d4, e1 - e2 should not exceed 100 ma. 4] the sum of all iol, for ports b3 - b5, c6 - c7 should not exceed 100 ma. 5] the sum of all iol, for ports b2, c4 - c5, d5 - d7 should not exceed 100 ma. if iol exceeds the test conditio n, vol may exceed the related sp ecification. pins ar e not guaranteed to sink current greater than the listed test condition. 4. although each i/o port can source more than the test condition s (20 ma at vcc = 5v, 10 ma at vcc = 3v) under steady state conditions (non-transient), t he following must be observed: so32, so24 and tqfn package: 1] the sum of all ioh, for all ports, should not exceed 400 ma. 2] the sum of all ioh, for ports b6 - b7, c0 - c1, d0 - d3, e0 should not exceed 150 ma. 3] the sum of all ioh, for ports b0 - b1, c2 - c3, d4, e1 - e2 should not exceed 150 ma. 4] the sum of all ioh, for ports b3 - b5, c6 - c7 should not exceed 150 ma. 5] the sum of all ioh, for ports b2, c4 - c5, d5 - d7 should not exceed 150 ma. if ioh exceeds the test condition, voh may exceed the relat ed specification. pins are not guaranteed to source current greater than the listed test condition. 5. minimum v cc for power-down is 2.5v. 6. the analog comparator propagation delay equals 1 comparator clock plus 30ns. see ?analog comparator? on page 215. for comparator clock definition. 25.3 external clock dr ive characteristics 25.3.1 calibrated internal rc oscillator accuracy 25.3.2 external clock drive waveforms figure 25-1. external clock drive waveforms v hysr analog comparator hysteresis voltage v cc = 5v, v in = 3v rising edge falling edge 20 0 30 65 mv mv i aclk analog comparator input leakage current v cc = 5v v in = v cc /2 -50 50 na t acid analog comparator propagation delay v cc = 2.7v v cc = 5.0v (6) (6) ns t a = -40 ? c to +105 ? c, v cc = 2.7v to 5.5v (unless otherwise noted) (continued) symbol parameter condition min. typ. max. units table 25-1. calibration accuracy of internal rc oscillator frequency v cc temperature calibration accuracy factory calibration 8.0 mhz 3v 25 ? c 10% user calibration 7.3 - 8.1 mhz 2.7v - 5.5v -40 ? c - 105 ? c1% 286 at90pwm216/316 [datasheet] 7710h?avr?07/2013 25.3.3 external clock drive 25.4 maximum speed vs. v cc maximum frequency is depending on v cc. as shown in figure 25-2 , the maximum frequency equals 8mhz when v cc is contained between 2.7v and 4.5v and equals 16mhz when v cc is contained between 4.5v and 5.5v. figure 25-2. maximum frequency vs. v cc , at90pwm216/316 25.5 pll characteristics. note: while connected to external clock or external oscillator, pll input frequency must be selected to provide outputs with frequency in accordance with driven parts of the circuit (cpu core, psc...) table 25-2. external clock drive symbol parameter v cc =2.7 - 5.5v v cc =4.5 - 5.5v units min. max. min. max. 1/t clcl oscillator frequency 0 8 0 16 mhz t clcl clock period 100 50 ns t chcx high time 40 20 ns t clcx low time 40 20 ns t clch rise time 1.6 0.5 ? s t chcl fall time 1.6 0.5 ? s ? t clcl change in period from one clock cycle to the next 22% safe operating area 16mhz 8mhz 2.7v 5.5v 4.5v table 25-3. pll characteristics - v cc = 2.7v to 5.5v (unless otherwise noted) symbol parameter min. typ. max. units pll if input frequency 0.5 1 2 mhz pll f pll factor 64 pll lt lock-in time 64 s 287 at90pwm216/316 [datasheet] 7710h?avr?07/2013 25.6 spi timing characteristics see figure 25-3 and figure 25-4 for details. note: in spi programming mode the minimum sck high/low period is: - 2 t clcl for f ck < 12 mhz - 3 t clcl for f ck >12 mhz figure 25-3. spi interface timing requirements (master mode) table 25-4. spi timing parameters description mode min. typ. max. 1 sck period master see table 16-4 ns 2 sck high/low master 50% duty cycle 3 rise/fall time master 3.6 4 setup master 10 5 hold master 10 6 out to sck master 0.5 ? t sck 7 sck to out master 10 8 sck to out high master 10 9 ss low to out slave 15 10 sck period slave 4 ? t ck 11 sck high/low (1) slave 2 ? t ck 12 rise/fall time slave 1.6 13 setup slave 10 14 hold slave t ck 15 sck to out slave 15 16 sck to ss high slave 20 17 ss high to tri-state slave 10 18 ss low to sck slave 2 ? t ck mo si (data output) sck (cpol = 1) mi so (data input) sck (cpol = 0) ss msb lsb lsb msb ... ... 61 22 3 45 8 7 288 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 25-4. spi interface timing requirements (slave mode) mi so (data output) sck (cpol = 1) mo si (data input) sck (cpol = 0) ss msb lsb lsb msb ... ... 10 11 11 12 13 14 17 15 9 x 16 289 at90pwm216/316 [datasheet] 7710h?avr?07/2013 25.7 adc characteristics table 25-5. adc characteristics - t a = -40 ? c to +105 ? c, v cc = 2.7v to 5.5v (unless otherwise noted) symbol parameter condition min typ max units resolution single ended conversion 10 bits differential conversion gain = 10x 8bits absolute accuracy (1) single ended conversion v ref = 2.56v adc clock = 1 mhz 34lsb single ended conversion v ref = 2.56v adc clock = 2 mhz 34lsb differential conversion gain = 10 v ref = 2.56v adc clock = 1 mhz 23lsb differential conversion gain = 10 v ref = 2.56v adc clock = 2 mhz 23lsb integral non-linearity (1) single ended conversion v cc = 4.5v, v ref = 2.56v adc clock = 2 mhz 0.8 1.2 lsb differential conversion gain = 10 v cc = 4.5v, v ref = 2.56v adc clock =2 mhz 0.8 1.5 lsb differential non-linearity (1) single ended conversion v cc = 4.5v, v ref = 4v adc clock = 2 mhz 0.8 1.2 lsb differential conversion gain = 10 v cc = 4.5v, v ref = 4v adc clock = 2 mhz 0.5 0.8 lsb zero error (offset) (1) single ended conversion v cc = 4.5v, v ref = 4v adc clock = 1 mhz -1 3 lsb differential conversion gain = 10 v cc = 4.5v, v ref = 4v adc clock = 2 mhz -0.5 0.5 lsb conversion time single conversion 8 320 s clock frequency 50 2000 khz av cc analog supply voltage v cc - 0.3 v cc + 0.3 v 290 at90pwm216/316 [datasheet] 7710h?avr?07/2013 25.8 dac characteristics 25.9 parallel programmi ng characteristics figure 25-5. parallel programming timing, including some general timing requirements v ref reference voltage single ended conversion 2.0 av cc v differential conversion 2.0 av cc - 0.6 v v in input voltage single ended conversion gnd v ref differential conversion -v ref /gain +v ref /gain input bandwidth single ended conversion 62.5 (2) khz differential conversion 4 (3) khz a ref internal voltage reference 2.46 2.56 2.66 v r ref reference input resistance 30 k ? r ain analog input resistance 100 m ? i hsm increased current consumption high speed mode single ended conversion 380 a 1. best results if codes >8 are used. 2. free running conversion at 8s. 3. 250khz when input signal is synchronous with amplifier clock. table 25-6. dac characteristics - t a = -40 ? c to +105 ? c, v cc = 2.7v to 5.5v (unless otherwise noted) symbol parameter condition min typ max units i out output current 100 a table 25-5. adc characteristics - t a = -40 ? c to +105 ? c, v cc = 2.7v to 5.5v (unless otherwise noted) (continued) symbol parameter condition min typ max units data & contol (data, xa0/1, bs1, bs2) xtal1 t xhxl t wlwh t dvxh t xldx t plwl t wlrh wr rdy/bsy pagel t phpl t plbx t bvph t xlwl t wlbx t bvwl wlrl 291 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 25-6. parallel programming timing, loading sequence with timing requirements (1) note: 1. the timing requirements shown in figure 25-5 (i.e., t dvxh , t xhxl , and t xldx ) also apply to loading operation. figure 25-7. parallel programming timing, reading sequence (within the same page) with timing requirements (1) note: 1. the timing requirements shown in figure 25-5 (i.e., t dvxh , t xhxl , and t xldx ) also apply to reading operation. xtal1 pagel t plxh xlxh t t xlph addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data bs1 xa0 xa1 load address (low byte) load data (low byte) load data (high byte) load data load address (low byte) xtal1 oe addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data bs1 xa0 xa1 load address (low byte) read data (low byte) read data (high byte) load address (low byte) t bvdv t oldv t xlol t ohdz table 25-7. parallel programming characteristics, v cc = 5v 10% symbol parameter min. typ. max. units v pp programming enable voltage 11.5 12.5 v i pp programming enable current 250 ? a t dvxh data and control valid before xtal1 high 67 ns t xlxh xtal1 low to xtal1 high 200 ns 292 at90pwm216/316 [datasheet] 7710h?avr?07/2013 notes: 1. t wlrh is valid for the write flash, write eeprom, wr ite fuse bits and write lock bits commands. 2. t wlrh_ce is valid for the chip erase command. t xhxl xtal1 pulse width high 150 ns t xldx data and control hold after xtal1 low 67 ns t xlwl xtal1 low to wr low 0 ns t xlph xtal1 low to pagel high 0 ns t plxh pagel low to xtal1 high 150 ns t bvph bs1 valid before pagel high 67 ns t phpl pagel pulse width high 150 ns t plbx bs1 hold after pagel low 67 ns t wlbx bs2/1 hold after wr low 67 ns t plwl pagel low to wr low 67 ns t bvwl bs1 valid to wr low 67 ns t wlwh wr pulse width low 150 ns t wlrl wr low to rdy/bsy low 0 1 ? s t wlrh wr low to rdy/bsy high (1) 3.7 5 ms t wlrh_ce wr low to rdy/bsy high for chip erase (2) 7.5 10 ms t xlol xtal1 low to oe low 0 ns t bvdv bs1 valid to data valid 0 250 ns t oldv oe low to data valid 250 ns t ohdz oe high to data tri-stated 250 ns table 25-7. parallel programming characteristics, v cc = 5v 10% (continued) symbol parameter min. typ. max. units 293 at90pwm216/316 [datasheet] 7710h?avr?07/2013 26. typical characteristi cs ? preliminary data the following charts show typical behavior. these figure s are not tested during manufacturing. all current con- sumption measurements are performed with all i/o pins conf igured as inputs and with internal pull-ups enabled. a sine wave generator with rail-to-rail output is used as clock source. all active- and idle current consumptio n measurements are done with all bits in the prr register set and thus, the corresponding i/o modules are turned off. also the a nalog comparator is disabl ed during these measurements. table 26-1 on page 297 and table 26-2 on page 297 show the additional current consumption compared to i cc active and i cc idle for every i/o module controlled by the power reduction register. see section 7.5 ?power reduction register? on page 37 for details. the power consumption in power-down mode is independent of clock selection. the current consumption is a function of several factors such as: operating voltage, operating frequency, loading of i/o pins, switching rate of i/o pins, code executed and ambient temperature. the dominating factors are operating voltage and frequency. the current drawn from capacitive loaded pi ns may be estimated (for one pin) as c l * v cc *f where c l = load capac- itance, v cc = operating voltage and f = average switching frequency of i/o pin. the parts are characterized at frequencies higher than test limits. parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. the difference between current consumption in power-down mode with watchdog timer enabled and power-down mode with watchdog timer disabled represents the differential current drawn by the watchdog timer. 26.1 active supply current figure 26-1. active supply current vs. frequency (0.1 - 1.0 mhz) active supply current vs. low frequency 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 3.0 v 2.7 v 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 frequency (mhz) i cc (ma) 294 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 26-2. active supply current vs . frequency (1 - 24 mhz) figure 26-3. active supply current vs. v cc (internal rc o scillator, 8 mhz) active supply current vs. frequency 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 3.0 v 2.7 v 0 5 10 15 20 25 30 0 5 10 15 20 25 frequency (mhz) i cc (ma) active supply current vs. v cc interna l rc oscilla tor, 8 mhz 105 c 85 c 25 c -40 c 0 1 2 3 4 5 6 7 8 9 22,533,544,555,5 v cc (v) i cc (ma) 295 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 26-4. active supply current vs. v cc (internal pll o scillator, 16 mhz) 26.2 idle supply current figure 26-5. idle supply current vs. frequency (0.1 - 1.0 mhz) active supply current vs. v cc interna l pll oscilla tor, 16 mhz 105 c 85 c 25 c -40 c 0 2 4 6 8 10 12 14 16 18 20 22,533,544,555,5 v cc (v) i cc (ma) idle supply current vs. low frequency 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 3.0 v 2.7 v 0 0,05 0,1 0,15 0,2 0,25 0,3 0,35 0,4 0,45 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 frequency (mhz) i cc (ma) 296 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 26-6. idle supply current vs. frequency (1 - 24 mhz) figure 26-7. iidle supply current vs. v cc (internal rc oscillator, 8 mhz) idle supply current vs. frequency 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 3.0 v 2.7 v 0 2 4 6 8 10 12 -1135791113151719212325 frequency (mhz) i cc (ma) idle supply current vs. v cc interna l rc oscilla tor, 8 mhz 105 c 85 c 25 c -40 c 0 0,5 1 1,5 2 2,5 3 3,5 4 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) i cc (ma) 297 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 26-8. idle supply current vs. v cc (internal pll os cillator, 16 mhz) 26.2.1 using the power reduction register the tables and formulas below can be used to calculate the additional current consumption for the different i/o modules in active and idle mode. the enabling or disab ling of the i/o modules are controlled by the power reduc- tion register. see ?power reduction register? on page 37 for details. idle supply current vs. v cc internal pll oscillator, 16 mhz 105 c 85 c 25 c -40 c 0 1 2 3 4 5 6 7 8 9 22,533,544,555,5 v cc (v) i cc (ma) table 26-1. additional current consumption for the different i/o modules (absolute values prr bit typical numbers v cc = 3v, f = 8mhz v cc = 5v, f = 16mhz prpsc2 350 ua 1.3 ma prpsc1 350 ua 1.3 ma prpsc0 350 ua 1.3 ma prtim1 300 ua 1.15 ma prtim0 200 ua 0.75 ma prspi 250 ua 0.9 ma prusart 550 ua 2 ma pradc 350 ua 1.3 ma table 26-2. additional current consumption (percentage) in active and idle mode prr bit additional current consumption compared to acti ve with external clock (see figure 26-1 and figure 26-2 ) additional current consumption compared to idle with external clock (see figure 26-5 and figure 26-6 ) prpsc2 10% 25% prpsc1 10% 25% prpsc0 10% 25% prtim1 8.5% 22% 298 at90pwm216/316 [datasheet] 7710h?avr?07/2013 it is possible to calculate the typical cu rrent consumption based on the numbers from table 26-2 for other v cc and frequency settings than listed in table 26-1 . 26.2.1.1 example 1 calculate the expected curr ent consumption in idle mode with u sart0, timer1, and spi enabled at v cc = 3.0v and f = 1mhz. from table 26-2 , third column, we see that we need to add 18% for the usart0, 26% for the spi, and 11% for the timer1 module. reading from figure 26-5 , we find that the idle current consumption is ~0,17ma at v cc = 3.0v and f = 1mhz. the total current consumptio n in idle mode with usart0 , timer1, and spi enabled, gives: 26.2.1.2 example 2 same conditions as in example 1, but in active mode instead. from table 26-2 , second column we see that we need to add 3.3% for the usart0, 4.8% for the spi , and 2.0% for the timer1 module. reading from figure 26-1 , we find that the active current consumption is ~0,6ma at v cc = 3.0v and f = 1mhz. the total current consumption in idle mode with usart0, timer1, and spi enabled, gives: 26.2.1.3 example 3 all i/o modules should be enabled. calculate the expected current consumption in active mode at v cc = 3.6v and f = 10mhz. we find the active current consumpti on without the i/o modules to be ~ 7.0ma (from figure 26-2 ). then, by using the numbers from table 26-2 - second column, we find the total current consumption: prtim0 4.3% 11% prspi 5.3% 14% prusart 15.6 36 pradc 10.5% 25% table 26-2. additional current consumption (percentage) in active and idle mode (continued) prr bit additional current consumption compared to acti ve with external clock (see figure 26-1 and figure 26-2 ) additional current consumption compared to idle with external clock (see figure 26-5 and figure 26-6 ) i cc total 0.17 ma 10.360.220.14 +++ ?? ? 0.29 ma ?? i cc total 0.6 ma 1 0.156 0.085 0.053 +++ ?? ? 0.77 ma ?? cc total 7.0 ma 1 0.1 0.1 0.1 0.085 0.043 0.053 0.156 0.105 ++++++++ ?? ? 12.2 ma ?? 299 at90pwm216/316 [datasheet] 7710h?avr?07/2013 26.3 power-down supply current figure 26-9. power-down supply current vs. v cc (watchdog timer disabled) figure 26-10. power-down supply current vs. v cc (watchdog timer enabled) power-down supply current vs. v cc wa tchdog timer disa bled 105 c 85 c 25 c -40 c 0 1 2 3 4 5 6 7 22,533,544,555,5 v cc (v) i cc (ua) power-down supply current vs. v cc wa tchdog timer ena bled 105 c 85 c 25 c -40 c 0 2 4 6 8 10 12 14 22,533,544,555,5 v cc (v) i cc (ua) 300 at90pwm216/316 [datasheet] 7710h?avr?07/2013 26.4 standby supply current figure 26-11. standby supply current vs. v cc (crystal oscillator) 26.5 pin pull-up figure 26-12. i/o pin pull-up re sistor current vs. input voltage (v cc = 5v) standby supply current vs. v cc full swing crystal oscillator 6 mhz xtal (ckopt) 4 mhz xtal (ckopt) 2 mhz xtal (ckopt) 16 mhz xtal 12 mhz xtal 0 50 100 150 200 250 300 350 400 450 500 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) t e m p l a t e t o b e c h a r a c t e r i z e d i/o pin (including pe1 & pe2) pull-up resistor current vs. input voltage vcc = 5.0 v 105 c 85 ? 25 ? -40 c -20 0 20 40 60 80 100 120 140 160 0123456 v op (v) i op (ua) 301 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 26-13. i/o pin pull-up re sistor current vs. input voltage (v cc = 2.7v) figure 26-14. reset pull-up resist or current vs. reset pin voltage (v cc = 5v) i/o pin (including pe1 & pe2) pull-up resistor current vs. input voltage vcc = 2.7 v 105 c 85 c 25 c -40 c -10 0 10 20 30 40 50 60 70 80 90 00,511,522,53 v op (v) i op (ua) pe0 and r eset pull-up resistor c urrent vs. input voltage vcc = 5.0 v 105 c 85 c 25 c -40 c 0 20 40 60 80 100 120 0123456 v op (v) i op (ua) 302 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 26-15. reset pull-up resist or current vs. reset pin voltage (v cc = 2.7v) 26.6 pin driver strength figure 26-16. i/o pin source current vs. output voltage (v cc = 5v) pe0 and reset pull-up resistor current vs. input voltage vcc = 2.7 v 105 c 85 c 25 c -40 c 0 10 20 30 40 50 60 70 0 0,5 1 1,5 2 2,5 3 v op (v) i op (ua) i/o pin (including pe1 & pe2) source current vs. output voltage vcc = 5.0 v 105 c 85 c 25 c -40 c 0 5 10 15 20 25 4 4,2 4,4 4,6 4,8 5 5,2 v oh (v) i oh (ma) 303 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 26-17. i/o pin source current vs. output voltage (v cc = 2.7v) figure 26-18. i/o pin sink current vs. output voltage (v cc = 5v) i/o pin (including pe1 & pe2) source current vs. output voltage vcc = 2.7 v 105 c 85 c 25 c -40 c 0 5 10 15 20 25 0 0,5 1 1,5 2 2,5 3 v oh (v) i oh (ma) i/o pin (including pe1 & pe2) sink current vs. output voltage vcc = 5.0 v 105 c 85 c 25 c -40 c -5 0 5 10 15 20 25 0 0,2 0,4 0,6 0,8 1 v ol (v) i ol (ma) 304 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 26-19. i/o pin sink current vs. output voltage (v cc = 2.7v) 26.7 pin thresholds and hysteresis figure 26-20. i/o pin input threshold voltage vs. v cc (vih, i/o pin read as '1') i/o pin (including pe1 & pe2) sink current vs. output voltage vcc = 2.7 v 105 c 85 c 25 c -40 c -5 0 5 10 15 20 25 00,511,522,53 v ol (v) i ol (ma) i/o pin (including pe1 & pe2) input threshold voltage vs. v cc v ih, io pin rea d a s '1' 105 c 85 c 25 c -40 c 0 0,5 1 1,5 2 2,5 22,533,544,555,5 v cc (v) threshold (v) 305 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 26-21. i/o pin input threshold voltage vs. v cc (vil, i/o pin read as '0') figure 26-22. i/o pin input hysteresisvoltage vs. v cc i/o pin (including pe1 & pe2) input threshold voltage vs. v cc v il, io pin rea d a s '0' 105 c 85 c 25 c -40 c 0 0,5 1 1,5 2 2,5 22,533,544,555,5 v cc (v) threshold (v) i/o pin input hysteresis vs. v cc 0 0.1 0.2 0.3 0.4 0.5 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) input hysteresis ( v) 85 c 25 c -40 c 306 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 26-23. reset input threshold voltage vs. v cc (vih, reset pin read as '1') figure 26-24. reset input threshold voltage vs. v cc (vil, reset pin read as '0') reset input threshold voltage vs. v cc v ih, reset pin rea d a s '1' 105 c 85 c 25 c -40 c 0 0,5 1 1,5 2 2,5 22,533,544,555,5 v cc (v) threshold (v) reset input threshold voltage vs. v cc v il, reset pin rea d a s '0' 105 c 85 c 25 c -40 c 0 0,5 1 1,5 2 2,5 22,533,544,555,5 v cc (v) threshold (v) 307 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 26-25. reset input pin hysteresis vs. v cc figure 26-26. xtal1 input threshold voltage vs. v cc (xtal1 pin read as '1') reset pin input hysteresis vs. v cc 105 c 85 c 25 c -40 c 0 0,1 0,2 0,3 0,4 0,5 0,6 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) input hysteresis (v) xtal1 input threshold voltage vs. v cc xtal1 pin read as "1" 105 c 85 c 25 c -40 c 0 0,5 1 1,5 2 2,5 3 3,5 4 22,533,544,555,5 v cc (v) threshold (v) 308 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 26-27. xtal1 input threshold voltage vs. v cc (xtal1 pin read as '0') figure 26-28. pe0 input threshold voltage vs. v cc (pe0 pin read as '1') xtal1 input threshold voltage vs. v cc xta l1 pin rea d a s "0" 105 c 85 c 25 c -40 c 0 0,5 1 1,5 2 2,5 3 3,5 4 22,533,544,555,5 v cc (v) threshold (v) pe0 input threshold voltage vs. v cc v ih, pe0 pin rea d a s '1' 105 c 85 c 25 c -40 c 0 0,5 1 1,5 2 2,5 3 3,5 4 22,533,544,555,5 v cc (v) threshold (v) 309 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 26-29. pe0 input threshold voltage vs. v cc (pe0 pin read as '0') 26.8 bod thresholds and analog comparator offset figure 26-30. bod thresholds vs. temper ature (bodlevel is 4.3v) pe0 input threshold voltage vs. v cc vil, pe0 pin read as '0' 105 c 85 c 25 c -40 c 0 0,5 1 1,5 2 2,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) threshold (v) bod thresholds vs. temperature bodlv is 4.3 v rising vcc falling vcc 4,28 4,3 4,32 4,34 4,36 4,38 4,4 4,42 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 temperature (c) threshold (v) 310 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 26-31. bod thresholds vs. temper ature (bodlevel is 2.7v) figure 26-32. analog comparator offset voltage vs. common mode voltage (v cc =5v) bod thresholds vs. temperature bodlv is 2.7 v rising vcc falling vcc 2,68 2,7 2,72 2,74 2,76 2,78 2,8 2,82 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 temperature (c) threshold (v) 85 c 25 c -40 c 150 200 250 300 350 400 450 500 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) template to be characterized 311 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 26-33. analog comparator offset voltage vs. common mode voltage (v cc =3v) 26.9 analog reference figure 26-34. aref voltage vs. v cc 85 c 25 c -40 c 150 200 250 300 350 400 450 500 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) template to be characterized aref voltage vs. v cc 105 c 85 c 25 ? -40 c 2,3 2,35 2,4 2,45 2,5 2,55 2,6 2 2,5 3 3,5 4 4,5 5 5,5 vcc (v) aref (v) 312 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 26-35. aref voltage vs. temperature 26.10 internal oscillator speed figure 26-36. watchdog oscillator frequency vs. v cc aref voltage vs. temperature 5.5 5 4.5 3 2.52 2.53 2.54 2.55 2.56 2.57 2.58 2.59 -60 -40 -20 0 20 40 60 80 100 120 temperature aref (v) watchdog oscillator frequency vs. operating voltage 105 c 85 c 25 c -40 c 96 98 100 102 104 106 108 110 22,533,544,555,5 v cc (v) f rc (khz) 313 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 26-37. calibrated 8 mhz rc oscillato r frequency vs. temperature figure 26-38. calibrated 8 mhz rc oscillator frequency vs. v cc calibrated 8mhz rc oscillator frequency vs. temperature 10000 cycles sampled w ith 250ns 7.4 7.5 7.6 7.7 7.8 7.9 8 8.1 8.2 8.3 8.4 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 temperature osccal (mhz ) 2.7 5 int rc oscillator frequency vs. operating voltage 10000 cycles sampled w ith 250ns 7.5 7.6 7.7 7.8 7.9 8 8.1 8.2 8.3 8.4 8.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) f rc (mhz) 105 85 25 -40 314 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 26-39. calibrated 8 mhz rc oscillato r frequency vs. osccal value 26.11 current consumpti on of peripheral units figure 26-40. brownout detector current vs. v cc 0 2 4 6 8 10 12 14 16 18 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 oscca l f rc (mhz) 105 85 25 -40 brownout detector current vs. v cc 105 c 85 c 25 c -40 c 0 5 10 15 20 25 30 35 40 45 22,533,544,555,5 v cc (v) i cc (ua) 315 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 26-41. adc current vs. v cc (adc at 50 khz) figure 26-42. aref current vs. v cc (adc at 1 mhz) aref vs. v cc adc at 50 khz 85 c 25 c -40 c 150 200 250 300 350 400 450 500 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) t e m p l a t e t o b e c h a r a c t e r i z e d aref vs. v cc adc at 1 mhz 85 ?c 25 ?c -40 ?c 0 20 40 60 80 100 120 140 160 180 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 316 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 26-43. analog comparator current vs. v cc figure 26-44. programming current vs. v cc analog comparator current vs. v cc 105 c 85 c 25 c -40 c 0 10 20 30 40 50 60 70 80 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) i cc (ua) programming current vs. v 85 ?c 25 ?c -40 ?c 0 2 4 6 8 10 12 14 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) cc 317 at90pwm216/316 [datasheet] 7710h?avr?07/2013 26.12 current consumption in reset and reset pulse width figure 26-45. reset supply current vs. v cc (0.1 - 1.0 mhz, excluding current through the reset pull-up) figure 26-46. reset supply current vs. v cc (1 - 24 mhz, excluding current through the reset pull-up) reset supply current vs. v cc excluding current through the reset pullup 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 3.0 v 2.7 v 0 0,02 0,04 0,06 0,08 0,1 0,12 0,14 0,16 0,18 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 frequency (mhz) i cc (ma) reset supply current vs. v cc excluding current through the reset pullup 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 3.0 v 2.7 v 0 0,5 1 1,5 2 2,5 3 3,5 4 0 5 10 15 20 25 frequency (mhz) i cc (ma) 318 at90pwm216/316 [datasheet] 7710h?avr?07/2013 figure 26-47. reset supply current vs. v cc (clock stopped, excluding current through the reset pull-up) figure 26-48. reset pulse width vs. v cc reset current vs. v cc (clock stopped) excluding current through the reset pullup 105 c 85 c 25 c -40 c -0,01 0 0,01 0,02 0,03 0,04 0,05 22,533,544,555,5 v cc (v) i cc (ma) reset pulse width vs. v cc ex t clo c k 1 mhz 105 c 85 c 25 c -40 c 0 200 400 600 800 1000 1200 1400 1600 0123456 v cc (v) pulsewidth (ns) 319 at90pwm216/316 [datasheet] 7710h?avr?07/2013 27. register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page (0xff) picr2h page 161 (0xfe) picr2l page 161 (0xfd) pfrc2b pcae2b pisel2b pelev2b pflte2b prfm2b3 prfm2b2 prfm2b1 prfm2b0 page 160 (0xfc) pfrc2a pcae2a pisel2a pelev2a pflte2a prfm2a3 prfm2a2 prfm2a1 prfm2a0 page 159 (0xfb) pctl2 ppre21 ppre20 pbfm2 paoc2b paoc2a parun2 pccyc2 prun2 page 159 (0xfa) pcnf2 pfifty2 palock2 plock2 pmode21 pmode20 pop2 pclksel2 pome2 page 156 (0xf9) ocr2rbh page 155 (0xf8) ocr2rbl page 155 (0xf7) ocr2sbh page 155 (0xf6) ocr2sbl page 155 (0xf5) ocr2rah page 155 (0xf4) ocr2ral page 155 (0xf3) ocr2sah page 155 (0xf2) ocr2sal page 155 (0xf1) pom2 pomv2b3 pomv2b2 pomv2b1 pomv2b0 pomv2a3 pomv2a2 pomv2a1 pomv2a0 page 162 (0xf0) psoc2 pos23 pos22 psync21 psync20 poen2d poen2b poen2c poen2a page 154 (0xef) picr1h page 161 (0xee) picr1l page 161 (0xed) pfrc1b pcae1b pisel1b pelev1b pflte1b prfm1b3 prfm1b2 prfm1b1 prfm1b0 page 160 (0xec) pfrc1a pcae1a pisel1a pelev1a pflte1a prfm1a3 prfm1a2 prfm1a1 prfm1a0 page 159 (0xeb) pctl1 ppre11 ppre10 pbfm1 paoc1b paoc1a parun1 pccyc1 prun1 page 158 (0xea) pcnf1 pfifty1 palock1 plock1 pmode11 pmode10 pop1 pclksel1 - page 156 (0xe9) ocr1rbh page 155 (0xe8) ocr1rbl page 155 (0xe7) ocr1sbh page 155 (0xe6) ocr1sbl page 155 (0xe5) ocr1rah page 155 (0xe4) ocr1ral page 155 (0xe3) ocr1sah page 155 (0xe2) ocr1sal page 155 (0xe1) reserved ? ? ? ? ? ? ? ? (0xe0) psoc1 ? ? psync11 psync10 ? poen1b ? poen1a page 153 (0xdf) picr0h page 161 (0xde) picr0l page 161 (0xdd) pfrc0b pcae0b pisel0b pelev0b pflte0b prfm0b3 prfm0b2 prfm0b1 prfm0b0 page 160 (0xdc) pfrc0a pcae0a pisel0a pelev0a pflte0a prfm0a3 prfm0a2 prfm0a1 prfm0a0 page 159 (0xdb) pctl0 ppre01 ppre00 pbfm0 paoc0b paoc0a parun0 pccyc0 prun0 page 157 (0xda) pcnf0 pfifty0 palock0 plock0 pmode01 pmode00 pop0 pclksel0 - page 155 (0xd9) ocr0rbh page 155 (0xd8) ocr0rbl page 155 (0xd7) ocr0sbh page 155 (0xd6) ocr0sbl page 155 (0xd5) ocr0rah page 155 (0xd4) ocr0ral page 155 (0xd3) ocr0sah page 155 (0xd2) ocr0sal page 155 (0xd1) reserved ? ? ? ? ? ? ? ? (0xd0) psoc0 ? ? psync01 psync00 ? poen0b ? poen0a page 153 (0xcf) reserved ? ? ? ? ? ? ? ? (0xce) eudr eudr7 eudr6 eudr5 eudr4 eudr3 eudr2 eudr1 eudr0 page 209 (0xcd) mubrrh mubrr15 mubrr014 mubrr13 mubrr12 mubrr011 mubrr010 mubrr9 mubrr8 page 214 (0xcc) mubrrl mubrr7 mubrr6 mubrr5 mubrr4 mubrr3 mubrr2 mubrr1 mubrr0 page 214 (0xcb) reserved ? ? ? ? ? ? ? ? (0xca) eucsrc ? ? ? ? fem f1617 stp1 stp0 page 213 (0xc9) eucsrb ? ? ? eusart eusbs ?emchbodr page 212 (0xc8) eucsra utxs3 utxs2 utxs1 utxs0 urxs3 urxs2 urxs1 urxs0 page 211 (0xc7) reserved ? ? ? ? ? ? ? ? (0xc6) udr udr07 udr06 udr05 udr04 udr03 udr02 udr01 udr00 page 209 & page 191 (0xc5) ubrrh ? ? ? ? ubrr011 ubrr010 ubrr09 ubrr08 page 195 (0xc4) ubrrl ubrr07 ubrr06 ubrr05 ubrr04 ubrr03 ubrr02 ubrr01 ubrr00 page 195 (0xc3) reserved ? ? ? ? ? ? ? ? (0xc2) ucsrc ? umsel0 upm01 upm00 usbs0 ucsz01 ucsz00 ucpol0 page 194 (0xc1) ucsrb rxcie0 txcie0 udrie0 rxen0 txen0 ucsz02 rxb80 txb80 page 193 (0xc0) ucsra rxc0 txc0 udre0 fe0 dor0 upe0 u2x0 mpcm0 page 191 (0xbf) reserved ? ? ? ? ? ? ? ? (0xbe) reserved ? ? ? ? ? ? ? ? 320 at90pwm216/316 [datasheet] 7710h?avr?07/2013 (0xbd) reserved ? ? ? ? ? ? ? ? (0xbc) reserved ? ? ? ? ? ? ? ? (0xbb) reserved ? ? ? ? ? ? ? ? (0xba) reserved ? ? ? ? ? ? ? ? (0xb9) reserved ? ? ? ? ? ? ? ? (0xb8) reserved ? ? ? ? ? ? ? ? (0xb7) reserved ? ? ? ? ? ? ? ? (0xb6) reserved ? ? ? ? ? ? ? ? (0xb5) reserved ? ? ? ? ? ? ? ? (0xb4) reserved ? ? ? ? ? ? ? ? (0xb3) reserved ? ? ? ? ? ? ? ? (0xb2) reserved ? ? ? ? ? ? ? ? (0xb1) reserved ? ? ? ? ? ? ? ? (0xb0) reserved ? ? ? ? ? ? ? ? (0xaf) ac2con ac2en ac2ie ac2is1 ac2is0 ? ac2m2 ac2m1 ac2m0 page 218 (0xae) ac1con ac1en ac1ie ac1is1 ac1is0 ac1ice ac1m2 ac1m1 ac1m0 page 217 (0xad) ac0con ac0en ac0ie ac0is1 ac0is0 - ac0m2 ac0m1 ac0m0 page 216 (0xac) dach - / dac9 - / dac8 - / dac7 - / dac6 - / dac5 - / dac4 dac9 / dac3 dac8 / dac2 page 247 (0xab) dacl dac7 / dac1 dac6 /dac0 dac5 / - dac4 / - dac3 / - dac2 / - dac1 / - dac0 / page 247 (0xaa) dacon daate dats2 dats1 dats0 - dala daoe daen page 246 (0xa9) reserved ? ? ? ? ? ? ? ? (0xa8) reserved ? ? ? ? ? ? ? ? (0xa7) reserved ? ? ? ? ? ? ? ? (0xa6) reserved ? ? ? ? ? ? ? ? (0xa5) pim2 - - pseie2 peve2b peve2a - - peope2 page 162 (0xa4) pifr2 - - psei2 pev2b pev2a prn21 prn20 peop2 page 163 (0xa3) pim1 - - pseie1 peve1b peve1a - - peope1 page 162 (0xa2) pifr1 - - psei1 pev1b pev1a prn11 prn10 peop1 page 163 (0xa1) pim0 - - pseie0 peve0b peve0a - - peope0 page 162 (0xa0) pifr0 - - psei0 pev0b pev0a prn01 prn00 peop0 page 163 (0x9f) reserved ? ? ? ? ? ? ? ? (0x9e) reserved ? ? ? ? ? ? ? ? (0x9d) reserved ? ? ? ? ? ? ? ? (0x9c) reserved ? ? ? ? ? ? ? ? (0x9b) reserved ? ? ? ? ? ? ? ? (0x9a) reserved ? ? ? ? ? ? ? ? (0x99) reserved ? ? ? ? ? ? ? ? (0x98) reserved ? ? ? ? ? ? ? ? (0x97) reserved ? ? ? ? ? ? ? ? (0x96) reserved ? ? ? ? ? ? ? ? (0x95) reserved ? ? ? ? ? ? ? ? (0x94) reserved ? ? ? ? ? ? ? ? (0x93) reserved ? ? ? ? ? ? ? ? (0x92) reserved ? ? ? ? ? ? ? ? (0x91) reserved ? ? ? ? ? ? ? ? (0x90) reserved ? ? ? ? ? ? ? ? (0x8f) reserved ? ? ? ? ? ? ? ? (0x8e) reserved ? ? ? ? ? ? ? ? (0x8d) reserved ? ? ? ? ? ? ? ? (0x8c) reserved ? ? ? ? ? ? ? ? (0x8b) ocr1bh ocr1b15 ocr1b14 ocr1b13 ocr1b12 ocr1b11 ocr1b10 ocr1b9 ocr1b8 page 119 (0x8a) ocr1bl ocr1b7 ocr1b6 ocr1b5 ocr1b4 ocr1b3 ocr1b2 ocr1b1 ocr1b0 page 119 (0x89) ocr1ah ocr1a15 ocr1a14 ocr1a13 ocr1a12 ocr1a11 ocr1a10 ocr1a9 ocr1a8 page 119 (0x88) ocr1al ocr1a7 ocr1a6 ocr1a5 ocr1a4 ocr1a3 ocr1a2 ocr1a1 ocr1a0 page 119 (0x87) icr1h icr115 icr114 icr113 icr112 icr111 icr110 icr19 icr18 page 119 (0x86) icr1l icr17 icr16 icr15 icr14 icr13 icr12 icr11 icr10 page 119 (0x85) tcnt1h tcnt115 tcnt114 tcnt113 tcnt112 tcnt111 tcnt110 tcnt19 tcnt18 page 119 (0x84) tcnt1l tcnt17 tcnt16 tcnt15 tcnt14 tcnt13 tcnt12 tcnt11 tcnt10 page 119 (0x83) reserved ? ? ? ? ? ? ? ? (0x82) tccr1c foc1a foc1b ? ? ? ? ? ? page 118 (0x81) tccr1b icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 page 117 (0x80) tccr1a com1a1 com1a0 com1b1 com1b0 ? ?wgm11wgm10 page 114 (0x7f) didr1 ? ? acmp0d amp0pd amp0nd adc10d/acmp1d adc9d/amp1pd adc8d/amp1nd page 239 (0x7e) didr0 adc7d adc6d adc5d adc4d adc3d/acmpmd adc2d/acmp2d adc1d adc0d page 239 (0x7d) reserved ? ? ? ? ? ? ? ? (0x7c) admux refs1 refs0 adlar ? mux3 mux2 mux1 mux0 page 235 (0x7b) adcsrb adhsm ? ? ? adts3 adts2 adts1 adts0 page 237 (0x7a) adcsra aden adsc adate adif adie adps2 adps1 adps0 page 236 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 321 at90pwm216/316 [datasheet] 7710h?avr?07/2013 (0x79) adch - / adc9 - / adc8 - / adc7 - / adc6 - / adc5 - / adc4 adc9 / adc3 adc8 / adc2 page 238 (0x78) adcl adc7 / adc1 adc6 / adc0 adc5 / - adc4 / - adc3 / - adc2 / - adc1 / - adc0 / page 238 (0x77) amp1csr amp1en - amp1g1 amp1g0 - amp1ts2 amp1ts1 amp1ts0 page 244 (0x76) amp0csr amp0en - amp0g1 amp0g0 - amp0ts2 amp0ts1 amp0ts0 page 243 (0x75) reserved ? ? ? ? ? ? ? ? (0x74) reserved ? ? ? ? ? ? ? ? (0x73) reserved ? ? ? ? ? ? ? ? (0x72) reserved ? ? ? ? ? ? ? ? (0x71) reserved ? ? ? ? ? ? ? ? (0x70) reserved ? ? ? ? ? ? ? ? (0x6f) timsk1 ? ?icie1 ? ? ocie1b ocie1a toie1 page 120 (0x6e) timsk0 ? ? ? ? ? ocie0b ocie0a toie0 page 93 (0x6d) reserved ? ? ? ? ? ? ? ? (0x6c) reserved ? ? ? ? ? ? ? ? (0x6b) reserved ? ? ? ? ? ? ? ? (0x6a) reserved ? ? ? ? ? ? ? ? (0x69) eicra isc31 isc30 isc21 isc20 isc11 isc10 isc01 isc00 page 75 (0x68) reserved ? ? ? ? ? ? ? ? (0x67) reserved ? ? ? ? ? ? ? ? (0x66) osccal ? cal6 cal5 cal4 cal3 cal2 cal1 cal0 page 29 (0x65) reserved ? ? ? ? ? ? ? ? (0x64) prr prpsc2 prpsc1 prpsc0 prtim1 prtim0 prspi prusart pradc page 37 (0x63) reserved ? ? ? ? ? ? ? ? (0x62) reserved ? ? ? ? ? ? ? ? (0x61) clkpr clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 page 33 (0x60) wdtcsr wdif wdie wdp3 wdce wde wdp2 wdp1 wdp0 page 48 0x3f (0x5f) sreg ithsvnz c page 11 0x3e (0x5e) sph sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 page 14 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 page 14 0x3c (0x5c) reserved ? ? ? ? ? ? ? ? 0x3b (0x5b) reserved ? ? ? ? ? ? ? ? 0x3a (0x5a) reserved ? ? ? ? ? ? ? ? 0x39 (0x59) reserved ? ? ? ? ? ? ? ? 0x38 (0x58) reserved ? ? ? ? ? ? ? ? 0x37 (0x57) spmcsr spmie rwwsb ? rwwsre blbset pgwrt pgers spmen page 256 0x36 (0x56) reserved ? ? ? ? ? ? ? ? 0x35 (0x55) mcucr spips ? ?pud ? ? ivsel ivce page 54 & page 62 0x34 (0x54) mcusr ? ? ? ? wdrf borf extrf porf page 44 0x33 (0x53) smcr ? ? ? ?sm2sm1sm0se page 35 0x32 (0x52) msmcr monitor stop mode control register reserved 0x31 (0x51) mondr monitor data register reserved 0x30 (0x50) acsr ? ac2if ac1if ac0if ? ac2o ac1o ac0o page 219 0x2f (0x4f) reserved ? ? ? ? ? ? ? ? 0x2e (0x4e) spdr spd7 spd6 spd5 spd4 spd3 spd2 spd1 spd0 page 171 0x2d (0x4d) spsr spif wcol ? ? ? ? ?spi2x page 171 0x2c (0x4c) spcr spie spe dord mstr cpol cpha spr1 spr0 page 169 0x2b (0x4b) reserved ? ? ? ? ? ? ? ? 0x2a (0x4a) reserved ? ? ? ? ? ? ? ? 0x29 (0x49) pllcsr - - - - - pllf plle plock page 31 0x28 (0x48) ocr0b ocr0b7 ocr0b6 ocr0b5 ocr0b4 ocr0b3 ocr0b2 ocr0b1 ocr0b0 page 93 0x27 (0x47) ocr0a ocr0a7 ocr0a6 ocr0a5 ocr0a4 ocr0a3 ocr0a2 ocr0a1 ocr0a0 page 93 0x26 (0x46) tcnt0 tcnt07 tcnt06 tcnt05 tcnt04 tcnt03 tcnt02 tcnt01 tcnt00 page 93 0x25 (0x45) tccr0b foc0a foc0b ? ? wgm02 cs02 cs01 cs00 page 91 0x24 (0x44) tccr0a com0a1 com0a0 com0b1 com0b0 ? ?wgm01wgm00 page 89 0x23 (0x43) gtccr tsm icpsel1 ? ? ? ? ? psrsync page 78 0x22 (0x42) eearh ? ? ? ? eear11 eear10 eear9 eear8 page 19 0x21 (0x41) eearl eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 page 19 0x20 (0x40) eedr eedr7 eedr6 eedr5 eedr4 eedr3 eedr2 eedr1 eedr0 page 19 0x1f (0x3f) eecr ? ? ? ? eerie eemwe eewe eere page 20 0x1e (0x3e) gpior0 gpior07 gpior06 gpior05 gpior04 gpior03 gpior02 gpior01 gpior00 page 24 0x1d (0x3d) eimsk ? ? ? ? int3 int2 int1 int0 page 76 0x1c (0x3c) eifr ? ? ? ? intf3 intf2 intf1 intf0 page 76 0x1b (0x3b) gpior3 gpior37 gpior36 gpior35 gpior34 gpior33 gpior32 gpior31 gpior30 page 24 0x1a (0x3a) gpior2 gpior27 gpior26 gpior25 gpior24 gpior23 gpior22 gpior21 gpior20 page 24 0x19 (0x39) gpior1 gpior17 gpior16 gpior15 gpior14 gpior13 gpior12 gpior11 gpior10 page 24 0x18 (0x38) reserved ? ? ? ? ? ? ? ? 0x17 (0x37) reserved ? ? ? ? ? ? ? ? 0x16 (0x36) tifr1 ? ?icf1 ? ? ocf1b ocf1a tov1 page 120 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 322 at90pwm216/316 [datasheet] 7710h?avr?07/2013 note: 1. for compatibility with future devices, reserved bits shou ld be written to zero if accesse d. reserved i/o memory addresse s should never be written. 2. i/o registers within the address range 0x00 - 0x1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be ch ecked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical one to them. note that , unlike most other avrs, the cbi and sbi instructions will only operate on the specified bit, and can th erefore be used on registers containing such status flags. the cbi and sbi instructions work wit h registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f must be used. when addressing i/o registers as data space using ld and st instructions, 0x20 mu st be added to these addre sses. the at90pwm216/316 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o space from 0x 60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. 0x15 (0x35) tifr0 ? ? ? ? ? ocf0b ocf0a tov0 page 94 0x14 (0x34) reserved ? ? ? ? ? ? ? ? 0x13 (0x33) reserved ? ? ? ? ? ? ? ? 0x12 (0x32) reserved ? ? ? ? ? ? ? ? 0x11 (0x31) reserved ? ? ? ? ? ? ? ? 0x10 (0x30) reserved ? ? ? ? ? ? ? ? 0x0f (0x2f) reserved ? ? ? ? ? ? ? ? 0x0e (0x2e) porte ? ? ? ? ? porte2 porte1 porte0 page 74 0x0d (0x2d) ddre ? ? ? ? ? dde2 dde1 dde0 page 74 0x0c (0x2c) pine ? ? ? ? ? pine2 pine1 pine0 page 74 0x0b (0x2b) portd portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 page 73 0x0a (0x2a) ddrd ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 page 73 0x09 (0x29) pind pind7 pind6 pind5 pind4 pind3 pind2 pind1 pind0 page 74 0x08 (0x28) portc portc7 portc6 portc5 portc4 portc3 portc2 portc1 portc0 page 73 0x07 (0x27) ddrc ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 page 73 0x06 (0x26) pinc pinc7 pinc6 pinc5 pinc4 pinc3 pinc2 pinc1 pinc0 page 73 0x05 (0x25) portb portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 page 73 0x04 (0x24) ddrb ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 page 73 0x03 (0x23) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 page 73 0x02 (0x22) reserved ? ? ? ? ? ? ? ? 0x01 (0x21) reserved ? ? ? ? ? ? ? ? 0x00 (0x20) reserved ? ? ? ? ? ? ? ? address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 323 at90pwm216/316 [datasheet] 7710h?avr?07/2013 28. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd ? rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd ? rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl ? rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd ? rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd ? rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd ? rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd ? rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl ? rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd ?? rd ? rr z,n,v 1 andi rd, k logical and register and constant rd ? rd ?? k z,n,v 1 or rd, rr logical or registers rd ? rd v rr z,n,v 1 ori rd, k logical or register and constant rd ?? rd v k z,n,v 1 eor rd, rr exclusive or registers rd ? rd ? rr z,n,v 1 com rd one?s complement rd ? 0xff ? rd z,c,n,v 1 neg rd two?s complement rd ? 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd ? rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd ? rd ? (0xff - k) z,n,v 1 inc rd increment rd ? rd + 1 z,n,v 1 dec rd decrement rd ? rd ? 1 z,n,v 1 tst rd test for zero or minus rd ? rd ? rd z,n,v 1 clr rd clear register rd ? rd ? rd z,n,v 1 ser rd set register rd ? 0xff none 1 mul rd, rr multiply unsigned r1:r0 ? rd x rr z,c 2 muls rd, rr multiply signed r1:r0 ? rd x rr z,c 2 mulsu rd, rr multiply signed with unsigned r1:r0 ? rd x rr z,c 2 fmul rd, rr fractional multiply unsigned r1:r0 ? (rd x rr) << 1 z,c 2 fmuls rd, rr fractional multiply signed r1:r0 ? (rd x rr) << 1 z,c 2 fmulsu rd, rr fractional multiply signed with unsigned r1:r0 ? (rd x rr) << 1 z,c 2 branch instructions rjmp k relative jump pc ?? pc + k + 1 none 2 ijmp indirect jump to (z) pc ? z none 2 jmp k direct jump pc ? knone3 rcall k relative subroutine call pc ? pc + k + 1 none 3 icall indirect call to (z) pc ? znone3 call k direct call pc ? knone4 ret subroutine return pc ? stack none 4 reti interrupt return pc ? stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc ?? pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc ? pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc ? pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc ? pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc ? pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc ? pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc ? pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc ? pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc ? pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc ? pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc ? pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc ? pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc ? pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc ? pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc ? pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n ? v= 0) then pc ? pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n ? v= 1) then pc ? pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc ? pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc ? pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc ? pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc ? pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc ? pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc ? pc + k + 1 none 1/2 brie k branch if interrupt enabled if ( i = 1) then pc ? pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc ? pc + k + 1 none 1/2 324 at90pwm216/316 [datasheet] 7710h?avr?07/2013 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) ? 1none2 cbi p,b clear bit in i/o register i/o(p,b) ? 0none2 lsl rd logical shift left rd(n+1) ? rd(n), rd(0) ? 0 z,c,n,v 1 lsr rd logical shift right rd(n) ? rd(n+1), rd(7) ? 0 z,c,n,v 1 rol rd rotate left through carry rd(0) ? c,rd(n+1) ? rd(n),c ? rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) ? c,rd(n) ? rd(n+1),c ? rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) ? rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) ? rd(7..4),rd(7..4) ? rd(3..0) none 1 bset s flag set sreg(s) ? 1 sreg(s) 1 bclr s flag clear sreg(s) ? 0 sreg(s) 1 bst rr, b bit store from register to t t ? rr(b) t 1 bld rd, b bit load from t to register rd(b) ? tnone1 sec set carry c ? 1c1 clc clear carry c ? 0 c 1 sen set negative flag n ? 1n1 cln clear negative flag n ? 0 n 1 sez set zero flag z ? 1z1 clz clear zero flag z ? 0 z 1 sei global interrupt enable i ? 1i1 cli global interrupt disable i ?? 0 i 1 ses set signed test flag s ? 1s1 cls clear signed test flag s ? 0 s 1 sev set twos complement overflow. v ? 1v1 clv clear twos complement overflow v ? 0 v 1 set set t in sreg t ? 1t1 clt clear t in sreg t ? 0 t 1 seh set half carry flag in sreg h ? 1h1 clh clear half carry flag in sreg h ? 0 h 1 data transfer instructions mov rd, rr move between registers rd ? rr none 1 movw rd, rr copy register word rd+1:rd ? rr+1:rr none 1 ldi rd, k load immediate rd ? knone1 ld rd, x load indirect rd ? (x) none 2 ld rd, x+ load indirect and post-inc. rd ? (x), x ? x + 1 none 2 ld rd, - x load indirect and pre-dec. x ? x - 1, rd ? (x) none 2 ld rd, y load indirect rd ? (y) none 2 ld rd, y+ load indirect and post-inc. rd ? (y), y ? y + 1 none 2 ld rd, - y load indirect and pre-dec. y ? y - 1, rd ? (y) none 2 ldd rd,y+q load indirect with displacement rd ? (y + q) none 2 ld rd, z load indirect rd ? (z) none 2 ld rd, z+ load indirect and post-inc. rd ? (z), z ? z+1 none 2 ld rd, -z load indirect and pre-dec. z ? z - 1, rd ? (z) none 2 ldd rd, z+q load indirect with displacement rd ? (z + q) none 2 lds rd, k load direct from sram rd ? (k) none 2 st x, rr store indirect (x) ?? rr none 2 st x+, rr store indirect and post-inc. (x) ?? rr, x ? x + 1 none 2 st - x, rr store indirect and pre-dec. x ? x - 1, (x) ? rr none 2 st y, rr store indirect (y) ? rr none 2 st y+, rr store indirect and post-inc. (y) ? rr, y ? y + 1 none 2 st - y, rr store indirect and pre-dec. y ? y - 1, (y) ? rr none 2 std y+q,rr store indirect with displacement (y + q) ? rr none 2 st z, rr store indirect (z) ? rr none 2 st z+, rr store indirect and post-inc. (z) ? rr, z ? z + 1 none 2 st -z, rr store indirect and pre-dec. z ? z - 1, (z) ? rr none 2 std z+q,rr store indirect with displacement (z + q) ? rr none 2 sts k, rr store direct to sram (k) ? rr none 2 lpm load program memory r0 ? (z) none 3 lpm rd, z load program memory rd ? (z) none 3 lpm rd, z+ load program memory and post-inc rd ? (z), z ? z+1 none 3 spm store program memory (z) ? r1:r0 none - in rd, p in port rd ? pnone1 out p, rr out port p ? rr none 1 push rr push register on stack stack ? rr none 2 pop rd pop register from stack rd ? stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 mnemonics operands description operation flags #clocks 325 at90pwm216/316 [datasheet] 7710h?avr?07/2013 wdr watchdog reset (see specific descr. for wdr/timer) none 1 break break for on-chip debug only none n/a mnemonics operands description operation flags #clocks 326 at90pwm216/316 [datasheet] 7710h?avr?07/2013 29. ordering information note: all packages are pb free, fully lhf note: this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering informa tion and minimum quantities. note: parts numbers are for shipping in sti cks (so) or in trays (qfn). these devices ca n also be supplied in tape and reel. plea se contact your local atmel sales office for detailed ordering information and minimum quantities. 30. package information speed (mhz) power supply ordering code package operation range 16 2.7 - 5.5v at90pwm316-16se so32 engineering samples 16 2.7 - 5.5v at90pwm316-16me qfn32 engineering samples 16 2.7 - 5.5v at90pwm216-16se so24 engineering samples 16 2.7 - 5.5v at90pwm316-16su so32 extended (-4 0 ? c to 105 ? c) 16 2.7 - 5.5v at90pwm316-16mu qfn32 extended (-4 0 ? c to 105 ? c) 16 2.7 - 5.5v at90pwm216-16su so24 extended (-4 0 ? c to 105 ? c) package type so24 24-lead, small outline package so32 32-lead, small outline package qfn32 32-lead, quad flat no lead 327 at90pwm216/316 [datasheet] 7710h?avr?07/2013 30.1 so24 328 at90pwm216/316 [datasheet] 7710h?avr?07/2013 30.2 so32 329 at90pwm216/316 [datasheet] 7710h?avr?07/2013 30.3 qfn32 330 at90pwm216/316 [datasheet] 7710h?avr?07/2013 331 at90pwm216/316 [datasheet] 7710h?avr?07/2013 31. errata at90pwm216/316 31.1 revision c ? dac driver linearity above 3.6v 1. dac driver linearity above 3.6v with 5v v cc , the dac driver linearity is poor when dac output level is above v cc -1v. at 5v, dac output for 1023 will be around 5v - 40mv. work around: use, when vcc=5v, v ref below v cc -1v or, when v ref =v cc =5v, do not uses codes above 800. 31.2 revision b ? dac driver linearity above 3.6v ? psc ocrxx register update according to plock2 usage 1. dac driver linearity above 3.6v with 5v v cc , the dac driver linearity is poor when dac output level is above v cc -1v. at 5v, dac output for 1023 will be around 5v - 40mv. work around: use, when vcc=5v, v ref below v cc -1v or, when v ref =v cc =5v, do not uses codes above 800. 2. psc ocrxx register update according to plock2 usage if the psc is clocked from pll, and if plock2 bit is changed at the same time as psc end of cycle occurs, and if ocrxx registers contents have been changed, then the updated ocrxx registers contents are not predictable. the cause is a synchronization issue between two regi sters in two different cloc k domains (pll clock which clocks psc and cpu clock). workaround: enable the psc end of cycle interrupt. at the beginning of psc eoc interrupt vector, change plock value (ocrxx registers can be updated outside the interrupt vector). this process guarantees that update and plock actions will not occur at the same moment. 332 at90pwm216/316 [datasheet] 7710h?avr?07/2013 31.3 revision a ? dac driver linearity above 3.6v ? psc ocrxx register update according to plock2 usage 1. dac driver linearity above 3.6v with 5v v cc , the dac driver linearity is poor when dac output level is above v cc -1v. at 5v, dac output for 1023 will be around 5v - 40mv. work around: use, when vcc=5v, v ref below v cc -1v or, when v ref =v cc =5v, do not uses codes above 800. 2. psc ocrxx register update according to plock2 usage if the psc is clocked from pll, and if plock2 bit is changed at the same time as psc end of cycle occurs, and if ocrxx registers contents have been changed, then the updated ocrxx registers contents are not predictable. the cause is a synchronization issue between two regi sters in two different cloc k domains (pll clock which clocks psc and cpu clock). workaround: enable the psc end of cycle interrupt. at the beginning of psc eoc interrupt vector, change plock value (ocrxx registers can be updated outside the interrupt vector). this process guarantees that update and plock actions will not occur at the same moment. 333 at90pwm216/316 [datasheet] 7710h?avr?07/2013 32. datasheet revision history for at90pwm216/316 please note that the referring page numbers in this section are referred to this document. the referring revision in this section are referring to the document revision. 32.1 rev. 7710h ? 07/2013 32.2 rev. 7710g ? 03/2013 1. removed ?1. history? chapter. 2. errata: ?revision c? on page 331 : errata added. ?revision b? on page 331 : errata added. ?revision a? on page 332 : errata updated. 1. applied the atmel new brand template that includes new logo and new addresses. 2. added note to the mlf/qfn package: the center gnd paddle has to be connected to gnd. 3. updated the figure 2-1 on page 2 . pin 18 changed to agnd instead of gnd. 4. updated the figure 2-2 on page 3 . pin 24 changed to agnd instead of gnd. 5. added note to the mlf/qfn package: the center gnd paddle has to be connected to gnd. 6. updated figure 5-2 on page 18 . 7. updated table 6-2 on page 26 . 8. updated ?mcu control register ? mcucr? on page 62 . added link for bit 4: ?configuring the pin? on page 57 . 9. corrected ?typos? in ?overview? on page 122 . 10. updated ?features? on page 122 . correct feature is: abnormality protection function, emergency input to force all outputs to low level. 11. updated ?center aligned mode? on page 130 . the label pscn00 and pscn01 are incorrect and are respectively replaced by pscn0 and pscn1. 12. updated the formula of ? the waveform frequency is defined by the following equation? in ?normal mode? on page 134 . 13. updated the formula of f average in ?enhanced mode? on page 135 . 14. updated ?input mode operation? on page 140 . added a link to the table 15-6 . 15. updated ?psc synchronization? on page 151 . the correct content: if the pscn has its parunn bit set, then it can start at the same time as pscn-1. 16. updated ?psc 1 control register ? pctl1? on page 158 . bit 4 and bit 3 linked to ?psc input configuration? on page 139 . 17. updated content description of bit 1 and bit 3 in ?psc 2 synchro and output co nfiguration ? psoc2? on page 154 . 18. updated ?output compare sa register ? ocrnsah and ocrnsal? on page 155 and ?output compare rb register ? ocrnrbh and ocrnrbl? on page 155 . the registers are r/w and not only w. 19. 20. updated ?overview? on page 215 . removed ?or clki/o/2? from the overview description. 21. updated figure 19-1 on page 216 , ?analog comparator block diagram(1)(2)? . 334 at90pwm216/316 [datasheet] 7710h?avr?07/2013 32.3 rev. 7710f ? 09/11 32.4 rev. 7710e ? 08/10 32.5 rev. 7710d 1. updated table page 2. 2. updated ?absolute maximum ratings*? on page 283 22. updated ?analog comparator status register ? acsr? on page 219 . added bit 3 - clkpll 23. updated ?amplifier? on page 239 . the correct content: ?the adc starting is done by setting the adsc (adc start conversion) bit in the adcsra register?. 24. updated figure 20-15 on page 240 and figure 20-16 on page 241 . changed ckadc to ckadc2. 25. updated ?psc output behavior during reset? on page 266 . if pscrv fuse equals 0 (programmed), the selected psc outputs will be forced to high state. if pscrv fuse equals 1 (unprogrammed), the selected psc outputs will be forced to low state. 26. updated ?electrical characteristics? on page 283 . added ?dac characteristics? on page 290 . 27. updated the table 25-1 on page 285 . replaced -40 ? c - 85 ? c with -40 ? c to 105 ? c 28. updated table 25-5 on page 289 . replaced v int parameter by a ref . min and max values updated. 1. updated table 8-1 on page 41 . added v por and v ccr in the table. 2. updated table 8-2 on page 42 . added min and max values for 101 and 010. 3. updated table 25-2 on page 286 . v cc = 1.8 - 5.5v columns removed. 1. updated ?port c (pc7..pc0)? on page 8 . 2. inserted a footnote ?at90pwm216 device is available in soic 24-pin package and does not have the d2a (dac output) brought out to i/0 pins.? on page 8 . 3. updated ?idle mode? on page 35 by removing the reference to acd. 4. updated ?voltage reference enable signals and start-up time? on page 44 . removed reference to acbg. 4. updated table 15-14 on page 157 ; table 15-15 on page 158 and table 15-16 on page 159 5. removed reference to the acckdiv from ?analog comparator? on page 215 and from ?register summary? on page 319 . 6. updated ?adc prescaler selection? on page 237 . 7. updated table 25-5 on page 289 with max and min value for internal voltage reference 8. removed ac2sade bit from ?register summary? on page 319 . 335 at90pwm216/316 [datasheet] 7710h?avr?07/2013 32.6 rev. 7710c 1. updated table page 2. 2. updated section ?interna l calibrated rc oscillator operat ing modes(1)(2)? on page 28. 3. updated section ?features? on page 245. 4. updated table in section ?electrical characteristics? on page 283. 5. added section section ?calibrated internal rc oscillator accuracy? on page 285. 6. updated table 25-5 on page 289 . 7. updated figure 26-36 on page 312 . 8. updated figure 26-37 on page 313 . 9. updated figure 26-38 on page 313 . 32.7 rev. 7710b 1. updated ?section ?in-system reprogra mmable flash program memory?, page 17 2. updated ? figure 5-1 on page 17 3. updated ? figure 6-1 on page 26 4. updated ? figure 6-7 on page 30 5. updated ? table 20-1 on page 227 6. updated ?section ?adc noise canceler?, page 228 7. updated ? table 20-6 on page 237 8. added ? table 20-7 on page 238 9. updated ?section ?amplifier?, page 239 10. updated ? figure 20-15 on page 240 11. added ? figure 20-16 on page 241 12. updated ? figure 20-17 on page 242 13. updated ?section ?amplifier 0 control and status register ? amp0csr?, page 243 14. updated ? table 20-9 on page 243 15. updated ?section ?amplifier 1control a nd status register ? amp1csr?, page 244 16. updated ? table 20-9 on page 243 17. updated ? table 20-11 on page 244 18. updated ? table 23-6 on page 263 19. updated ? table 23-7 on page 263 20. updated ? table 23-8 on page 263 21. updated ?section ?dc characteristics?, page 284 22. updated ? table 25-5 on page 289 23. updated ?section ?example 1?, page 298 24. updated ?section ?example 2?, page 298 25. updated ?section ?example 3?, page 298 26. added ? figure 26-22 on page 305 27. updated ?section ?instruction set summary?, page 323 28. added ?section ?errata at90pwm216/316?, page 331 32.8 rev. 7710a 1. document creation. 336 at90pwm216/316 [datasheet] 7710h?avr?07/2013 i at90pwm216/316 [datasheet] 7710h?avr?07/2013 table of contents 1 disclaimer ............... .............. .............. .............. .............. .............. ............ 2 2 pin configurations .......... ................. ................ .............. .............. ............ 2 2.1 pin descriptions ......... ......................................................................................5 3 overview ................. .............. .............. .............. .............. .............. ............ 6 3.1 block diagram ...................................................................................................7 3.2 pin descriptions ........... ......................................................................................8 3.3 about code examples .......................................................................................9 4 avr cpu core ............... ................ ................. .............. .............. ............ 10 4.1 introduction ......................................................................................................10 4.2 architectural overview .....................................................................................10 4.3 alu ? arithmetic logic unit .............................................................................11 4.4 status register ................................................................................................11 4.5 general purpose register file ........................................................................12 4.6 stack pointer ...................................................................................................14 4.7 instruction execution timing ...........................................................................14 4.8 reset and interrupt handling ...........................................................................15 5 memories ............... .............. .............. .............. .............. .............. ............ 17 5.1 in-system reprogrammable flash program memory .....................................17 5.2 sram data memory ........................................................................................17 5.3 eeprom data memory . ................ ................. ............. ............ ............. ..........19 5.4 i/o memory ......................................................................................................23 5.5 general purpose i/o registers .......... .............................................................24 6 system clock .......... ................ ................. ................ ................. .............. 25 6.1 clock systems and their distribution .. .............................................................25 6.2 clock sources .................................................................................................26 6.3 default clock source .......................................................................................27 6.4 low power crystal oscillator ...........................................................................27 6.5 calibrated internal rc oscillator .....................................................................28 6.6 pll ..................................................................................................................29 6.7 128 khz internal oscillator ..............................................................................31 6.8 external clock .................................................................................................31 6.9 clock output buffer .........................................................................................32 6.10 system clock prescaler ..................................................................................32 ii at90pwm216/316 [datasheet] 7710h?avr?07/2013 7 power management and sleep modes .... ................ ................. ............ 35 7.1 idle mode .........................................................................................................35 7.2 adc noise reduction mode ............................................................................36 7.3 power-down mode ...........................................................................................36 7.4 standby mode .................................................................................................36 7.5 power reduction register ...............................................................................37 7.6 minimizing power consumption ......................................................................38 8 system control and r eset ................... .............. .............. ............ .......... 40 8.1 resetting the avr ...........................................................................................40 8.2 reset sources .................................................................................................40 8.3 power-on reset ...............................................................................................41 8.4 external reset .................................................................................................42 8.5 brown-out detection ........................................................................................42 8.6 watchdog reset ..............................................................................................43 8.7 mcu status register ? mcusr ......................................................................44 8.8 internal voltage reference ..............................................................................44 8.9 watchdog timer ..............................................................................................45 9 interrupts ............... .............. .............. .............. .............. .............. ............ 51 9.1 interrupt vectors in at 90pwm216/316 ...........................................................51 10 i/o-ports ......... ................ ................ ................. .............. .............. ............ 56 10.1 introduction ......................................................................................................56 10.2 ports as general digital i/o .............................................................................56 10.3 alternate port functions ..................................................................................61 10.4 register description for i/o-ports ....................................................................73 11 external interrupts ........ ................ ................. .............. .............. ............ 75 12 timer/counter0 and timer/counter1 pr escalers .............. ............ ....... 77 13 8-bit timer/counter0 with pw m .................... .............. .............. ............ 79 13.1 overview ..........................................................................................................79 13.2 timer/counter clock sources .........................................................................80 13.3 counter unit ....................................................................................................80 13.4 output compare unit .......................................................................................81 13.5 compare match output unit ............................................................................83 13.6 modes of operation .........................................................................................84 13.7 timer/counter timing dia grams ......................................................................88 13.8 8-bit timer/counter register description ........................................................89 iii at90pwm216/316 [datasheet] 7710h?avr?07/2013 14 16-bit timer/counter1 with pw m .................. .............. .............. ............ 95 14.1 overview ..........................................................................................................95 14.2 accessing 16-bit registers ..............................................................................97 14.3 timer/counter clock sources .......................................................................100 14.4 counter unit ..................................................................................................101 14.5 input capture unit .........................................................................................102 14.6 output compare units ...................................................................................103 14.7 compare match output unit ..........................................................................105 14.8 modes of operation .......................................................................................106 14.9 timer/counter timing dia grams ....................................................................113 14.10 16-bit timer/counter re gister description ....................................................114 15 power stage controller ? (psc0, psc1 & psc2) ............. ................. 122 15.1 features ........................................................................................................122 15.2 overview ........................................................................................................122 15.3 psc description ............................................................................................123 15.4 signal description ..........................................................................................125 15.5 functional description ...................................................................................127 15.6 update of values ...........................................................................................132 15.7 enhanced resolution ....................................................................................132 15.8 psc inputs ....................................................................................................135 15.9 psc input mode 1: stop signal, jump to opposite dead-time and wait .....141 15.10 psc input mode 2: stop signal, exec ute opposite dead-time and wait .....142 15.11 psc input mode 3: stop signal, exec ute opposite while fault active ...........143 15.12 psc input mode 4: deactivate output s without changing timing. ..................144 15.13 psc input mode 5: stop signal and insert dead-time ..................................144 15.14 psc input mode 6: stop signal, jump to opposite dead-time and wait. ....145 15.15 psc input mode 7: halt psc and wait for software action ..........................145 15.16 psc input mode 8: edge retrigger psc .......................................................146 15.17 psc input mode 9: fixed frequen cy edge retrigger psc ...........................147 15.18 psc input mode 14: fixed frequency edge retrigger psc and disactivate output 148 15.19 psc2 outputs ................................................................................................150 15.20 analog synchronization .................................................................................150 15.21 interrupt handling ..........................................................................................151 15.22 psc synchronization .....................................................................................151 15.23 psc clock sources .......................................................................................152 15.24 interrupts .......................................................................................................153 iv at90pwm216/316 [datasheet] 7710h?avr?07/2013 15.25 psc register definition .................................................................................153 15.26 psc2 specific register .................................................................................162 16 serial peripheral interface ? spi ............ ................ ................. ............ 165 16.1 features ........................................................................................................165 16.2 ss pin functionality ......................................................................................168 16.3 data modes ...................................................................................................171 17 usart .............. ................ ................. .............. .............. .............. .......... 173 17.1 features ........................................................................................................173 17.2 overview ........................................................................................................173 17.3 clock generation ...........................................................................................174 17.4 serial frame ..................................................................................................177 17.5 usart initialization .......................................................................................178 17.6 data transmission ? usart transmitte r .....................................................179 17.7 data reception ? usart receiver ..............................................................182 17.8 asynchronous data reception ......................................................................187 17.9 multi-processor communication mode ..........................................................190 17.10 usart register description .........................................................................191 17.11 examples of baud rate setting .....................................................................196 18 eusart (extended usart) .. ................. ................ ................. ............ 200 18.1 features ........................................................................................................200 18.2 overview ........................................................................................................200 18.3 serial frames ................................................................................................201 18.4 configuring the eusart ...............................................................................206 18.5 data reception ? eusart receiver ............................................................207 18.6 eusart registers description .......... ...........................................................209 19 analog comparator ............ .............. .............. .............. .............. .......... 215 19.1 overview ........................................................................................................215 19.2 analog comparator register description ......................................................216 20 analog to digital converter - adc ................ .............. .............. .......... 222 20.1 features ........................................................................................................222 20.2 operation .......................................................................................................224 20.3 starting a conversion ....................................................................................224 20.4 prescaling and conversion timing ................................................................225 20.5 changing channel or reference selection ...................................................227 20.6 adc noise canceler .....................................................................................228 v at90pwm216/316 [datasheet] 7710h?avr?07/2013 20.7 adc conversion result .................................................................................232 20.8 adc register description ..............................................................................234 20.9 amplifier .........................................................................................................239 20.10 amplifier control registers ............................................................................243 21 digital to analog converter - dac ................ .............. .............. .......... 245 21.1 features ........................................................................................................245 21.2 operation .......................................................................................................246 21.3 starting a conversion ....................................................................................246 21.4 dac register description ..............................................................................246 22 debugwire on-chip debug s ystem ............. .............. .............. .......... 249 22.1 features ........................................................................................................249 22.2 overview ........................................................................................................249 22.3 physical interface ..........................................................................................249 22.4 software break points ...................................................................................250 22.5 limitations of debugwire .............................................................................250 22.6 debugwire related register in i/o me mory ................................................250 23 boot loader support ? read-while-w rite self-programming ......... 251 23.1 boot loader features ....................................................................................251 23.2 application and boot loader flash sections .................................................251 23.3 read-while-write and no read-while-write flash se ctions ........................251 23.4 boot loader lock bits ...................................................................................254 23.5 entering the boot loader program ................................................................255 23.6 addressing the flash during self-pro gramming ...........................................257 23.7 self-programming the flash ..........................................................................258 24 memory programming ........... ................. ................ ................. ............ 265 24.1 program and data memory lock bits ...........................................................265 24.2 fuse bits ........................................................................................................266 24.3 psc output behavior during reset ... ...........................................................266 24.4 signature bytes .............................................................................................268 24.5 calibration byte .............................................................................................268 24.6 parallel programming pa rameters, pin mapping, an d commands ...............268 24.7 serial programming pin mapping .......... ........................................................270 24.8 parallel programming ......................... ...........................................................271 24.9 serial downloading ........................................................................................279 25 electrical characteristics .. .............. .............. .............. .............. .......... 283 vi at90pwm216/316 [datasheet] 7710h?avr?07/2013 25.1 absolute maximum ratings* .........................................................................283 25.2 dc characteristics .........................................................................................284 25.3 external clock drive characteristics .............................................................285 25.4 maximum speed vs. v cc .................................................................................................................... 286 25.5 pll characteristics. ......................................................................................286 25.6 spi timing characteristics ............................................................................287 25.7 adc characteristics ......................................................................................289 25.8 dac characteristics ......................................................................................290 25.9 parallel programming char acteristics ...........................................................290 26 typical characteristics ? preliminary data ........... ................. ............ 293 26.1 active supply current ....................................................................................293 26.2 idle supply current ........................................................................................295 26.3 power-down supply current .........................................................................299 26.4 standby supply current ................................................................................300 26.5 pin pull-up .....................................................................................................300 26.6 pin driver strength ........................................................................................302 26.7 pin thresholds and hysteresis ......................................................................304 26.8 bod thresholds and anal og comparator offset ..........................................309 26.9 analog reference ..........................................................................................311 26.10 internal oscillator speed ...............................................................................312 26.11 current consumption of peripheral units ......................................................314 26.12 current consumption in reset and re set pulse width ..................................317 27 register summary .............. .............. .............. .............. .............. .......... 319 28 instruction set summary ..... .............. .............. .............. .............. ........ 323 29 ordering information ........... .............. .............. .............. .............. ........ 326 30 package information ............ .............. .............. .............. .............. ........ 326 30.1 so24 .............................................................................................................327 30.2 so32 .............................................................................................................328 30.3 qfn32 ...........................................................................................................329 31 errata at90pwm216/316 .......... ................ ................ ................. .......... 331 31.1 revision c .....................................................................................................331 31.2 revision b .....................................................................................................331 31.3 revision a .....................................................................................................332 32 datasheet revision history for at90pw m216/316 .......... ................. 333 32.1 rev. 7710h ? 07/2013 333 32.2 rev. 7710g ? 03/2013 333 32.3 rev. 7710f ? 09/11 334 32.4 rev. 7710e ? 08/10 334 32.5 rev. 7710d 334 32.6 rev. 7710c 335 32.7 rev. 7710b 335 32.8 rev. 7710a 335 atmel corporation 1600 technology drive san jose, ca 95110 usa tel: (+1) (408) 441-0311 fax: (+1) (408) 487-2600 www.atmel.com atmel asia limited unit 01-5 & 16, 19f bea tower, millennium city 5 418 kwun tong roa kwun tong, kowloon hong kong tel: (+852) 2245-6100 fax: (+852) 2722-1369 atmel munich gmbh business campus parkring 4 d-85748 garching b. munich germany tel: (+49) 89-31970-0 fax: (+49) 89-3194621 atmel japan g.k. 16f shin-osaki kangyo bldg 1-6-4 osaki, shinagawa-ku tokyo 141-0032 japan tel: (+81) (3) 6417-0300 fax: (+81) (3) 6417-0370 ? 2013 atmel corporation. all rights reserved. / rev.: 7710h?avr?07/2013 disclaimer: the information in this document is provided in co nnection with atmel products. no lic ense, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. exc ept as set forth in the atmel terms and conditions of sales locat ed on the atmel website, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its products including, but not li mited to, the implied warranty of merchantability, fitness for a particular purpose, or non-infringement. in no event shall atmel be liable for any d irect, indirect, consequential, punitive, special or incide ntal damages (including, without limitation, damages for loss and profits, business i nterruption, or loss of information) arising out of the us e or inability to use this document, even if at mel has been advised of the possibility of suc h damages. atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the ri ght to make changes to specifications and products descriptions at any time without notice. atmel does not make any commitment to update th e information contained herein. un less specifically provided oth erwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel products are not intended, authorized, or warranted for use as components in applications intend ed to support or sustain life. atmel ? , atmel logo and combinations thereof, enabling unlimited possibilities ? , and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others. |
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